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Browse Prior Art Database

Low Skew Clock Tree Buffer Arrangement

IP.com Disclosure Number: IPCOM000105201D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 1 page(s) / 45K

Publishing Venue

IBM

Related People

Johnson, DWJ: AUTHOR

Abstract

Disclosed is a method of reducing skew in a clock tree. It is necessary to have simultaneous and controllable arrivals of clock signals at latches. Any degradation in simultaneous arrival is clock arrival is clock skew, and results in direct degradation of cycle time. Adding any additional logic to the clock path increases delay and provides a source of clock skew through delay variation.

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This is the abbreviated version, containing approximately 73% of the total text.

Low Skew Clock Tree Buffer Arrangement

       Disclosed is a method of reducing skew in a clock tree.
It is necessary to have simultaneous and controllable arrivals
of clock signals at latches.  Any degradation in simultaneous
arrival is clock arrival is clock skew, and results in direct
degradation of cycle time.  Adding any additional logic to the
clock path increases delay and provides a source of clock skew
through delay variation.

       When producing multiple clocks for distribution either
on-chip (clock tree) or off-chip, there may be logic necessary
in the clock path.  This can include gating signals, divide
circuits to lower the frequency of the clock, splitters or
choppers to change the clock shape, and so on.

       There may be a need to have multiple classes of clock by
having separate gates, by developing multiple frequencies, etc.
Delay variation between paths becomes more uncontrollable.

       A layer of registers (latches) immediately at the exit of
the clock tree going either off-chip or to the latches can be
added to realign the clock.  These are tied to the raw clock
coming into the chip.  Any skew in logic or the original clock
tree is thus removed.

       Wide latches such as octal latches should be used where
possible.  These are generally designed with better delay and
skew control.  This also reduces the number of clock loads, and
thus improves the delay caused by distributing the alignment
latch clock by decrea...