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Browse Prior Art Database

Array Built-In Self-Test Design with a Flag Pin

IP.com Disclosure Number: IPCOM000105237D
Original Publication Date: 1993-Jul-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Mifsud, JP: AUTHOR

Abstract

At present, all ABIST (Array Built-In Self-Test) designs were customized for each SRAM configuration (number of words and bits), and the number of ABIST cycles required to apply all the patterns to the MUT (Memory Under Test) is specific to each configuration. The ABIST test time (number of cycle x cycle time) MUST be explicitly defined for each SRAM and no commonality is possible.

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This is the abbreviated version, containing approximately 89% of the total text.

Array Built-In Self-Test Design with a Flag Pin

      At present, all ABIST (Array Built-In Self-Test) designs were
customized for each SRAM configuration (number of words and bits),
and the number of ABIST cycles required to apply all the patterns to
the MUT (Memory Under Test) is specific to each configuration.  The
ABIST test time (number of cycle x cycle time) MUST be explicitly
defined for each SRAM and no commonality is possible.

      Each embedded SRAM also requires the implementation of a
specific counter on the chip.  For large SRAMs  more than
3,000,000,000 ABIST cycles may be required, and a large counter (more
than 20 bits) also needs to be integrated.  For populated chips, the
area consumed by the counter is a significant area overhead (0.2 -
0.5 mm2).

      As illustrated in the figure, the new idea disclosed herein
below consists in the implementation in the SRAM of a new output pin
(FLAG), signalling the ABIST completion.  Already, an internal signal
of the "ABIST state machine" called  NOOP, is set to "1" when the
ABIST is finished and puts the ABIST in a "WAIT" state.  This NOOP
signal can be connected to the output FLAG pin, to propagate this
information to indicate that the SRAM test is completed.  At the chip
level, all the FLAG pins can be "ANDed" to propagate the information
that all the ABISTs (that were run in parallel) are finished.  In
"SYSTEM" mode, the FLAG pin can "gate" the clock distribution
network, indicating thereby...