Browse Prior Art Database

Design of a Switch to Manage I-Prefetching

IP.com Disclosure Number: IPCOM000105238D
Original Publication Date: 1993-Jul-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 92K

Publishing Venue

IBM

Related People

Rechtschaffen, R: AUTHOR

Abstract

In order to organize a prefetching mechanism within the L2 cache directory that can handle BWG's with ease a means for switch predecessor level indicators without maintaining successor-predecessor pointers is helpful. The approach is is disclosed.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Design of a Switch to Manage I-Prefetching

      In order to organize a prefetching mechanism within the L2
cache directory that can handle BWG's with ease a means for switch
predecessor level indicators without maintaining
successor-predecessor pointers is helpful.  The approach is is
disclosed.

      Consider a framework in which the L2 can perform I-CACHE
prefetching for the individual processors that are attached to it.
The steps involved in the process is to record the succession of
distinct I-LINES that miss from a purged I-CACHE within the
L2-DIRECTORY.  The manner of recording, within the L2, is to
associate with each L1-I-LINE the successor I-LINES as levels.  The
levels contain the addresses of EXITS-FROM-AN-I-LINE and the
addresses indicate the next-I-LINE accessed, the DW.X (Double Word
Index) within that line that should be brought in first, and the
LEVEL INDICATOR (LI) within LEVELS associated with the TARGET I-LINE
that is identified with the putative EXIT-FROM-THE-TARGET I-LINE.

The following schematic illustrates the relationship between these
quantities:

    HERE LINE D IS ENTERED WITH AN INDICATION THAT THE EXIT IS
    ASSOCIATED WITH ITS SECOND ENTRY POINT, THE EXIT TO LINE B,
    WILL BE USED.  LINE B WILL USE THE EXIT ASSOCIATED WITH ITS
    THIRD ENTRY POINT.
|
|
|          LINE D
|                                             LINE B
|   LEVEL#1   LINE D.EXIT.1 (3)
--> LEVEL#2   LINE D.EXIT.2 (1)----->    LEVEL#1   LINE B.EXIT.1
(3)---->
    LEVEL#3   LINE D.EXIT.3 (2)          LEVEL#2   LINE B.EXIT.2 (1)
    LEVEL#4   LINE D.EXIT.4 (2)          LEVEL#3   LINE B.EXIT.3 (2)
                                         LEVEL#4   LINE B.EXIT.4 (2)

These relationships as to the assignment levels to entry points is
derived from the initial miss sequence.  If some of the lines contain
variable action/target branches, what we call TYPE B branches, then a
branch wrong guess (BWG) disturbs these entry/exit relationships.

A DESIGN OF A SWITCH TO MANAGE I-PREFETCHING - When a BWG occurs
within a line it is possible that the LEVEL INDICATOR within the
predecessor line may have to be changed to reflect the new EXIT
associated with the line for that entry.  This failure to reflect the
impact of the BWG is what makes the prefetching information worthless
in these cases.  The manner of alteration, in the predecessor, for a
BWG in the successor requires a successor-predecessor pointer.  This
becomes cumbersome when a single line has multiple predecessors and
multiple entry-exit relationships are impacted by the BWG.

      A simpler approach...