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Verification and Implementation of Post-Manufacturing Chip Design Change

IP.com Disclosure Number: IPCOM000105241D
Original Publication Date: 1993-Jul-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 6 page(s) / 365K

Publishing Venue

IBM

Related People

Bellwood, TA: AUTHOR [+3]

Abstract

A process for verifying and implementing logic changes on a chip. The process allows a designer to quickly identify a chip logic change which considers both timing and net accessibility before implementing the change.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 17% of the total text.

Verification and Implementation of Post-Manufacturing Chip Design Change

      A process for verifying and implementing logic changes on a
chip.  The process allows a designer to quickly identify a chip logic
change which considers both timing and net accessibility before
implementing the change.

      Engineering system test of a mainframe machine will uncover
logic problems in a chip design that are not identified by system
simulation.  The current procedure for correcting a logic problem is
to implement an Engineering Change (EC) on the chip or module or to
generate a Temporary Fix (TX) to the module.  Either of these routes
will allow the TCM or chip designer to implement a fix to the logic
and allow system test to continue on the machine.  The turn around
time required to implement an EC on a chip can take a significant
amount of time and is not guaranteed to work until the repaired chip
is placed back into the machine and tested.  The length of the repair
process and the uncertainty of whether the logic fix will work add a
significant time and cost to the development of a machine.  A repair
process which allows the designer to turn around a logic fix quickly
and with a greater level of certainty that the fix will work would
have a significant positive effect on the cycle time for machine
delivery.

      The current methodology for making repairs on chip is called
Chip EX (Engineering Fix).  This methodology requires a high-level of
human intervention, has very few software tools to assist the chip
designer and is prone to error.  Logic descriptions of a chip design
are marked up on paper by the chip designer and are passed to the GL1
designer who attempts to implement the logic changes in the GL1 based
on the mark-ups.  Spare logic is generally unavailable on these chips
so any logical changes consist mostly of tieing up or tieing down
signal lines.  The GL1 designer must then hand the GL1 mark-ups to
the person who operates the Laser Bore, Focused Ion Beam, and LCVD
(Laser Chemical Vapor Deposition) machines to get the marked up
physical changes implemented in the actual chip.  The chip is tested
after the logical fix has been applied to determine if the changes
are what the designer originally wanted and to insure the changes did
not negatively impact any other function on the chip.  No process or
tools are available which will allow the chip designer to perform
analysis on a proposed Chip EX to determine that the EX is logically
correct for the problem and will be physically possible to implement.
Delay considerations are also not taken into account to insure that
the Chip EX will not negatively impact the timing of electrical nets
affected by the fix.  The process and tools support currently defined
for Chip EX have design iterations inherently built into the process,
reducing the effectiveness of the process to quickly turn around chip
repairs and adding significantly to the overall design time for a
mac...