Browse Prior Art Database

Gonzales-Liang Control Architecture for a Graphics Processor

IP.com Disclosure Number: IPCOM000105260D
Original Publication Date: 1993-Jul-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 6 page(s) / 314K

Publishing Venue

IBM

Related People

Chau, JB: AUTHOR [+3]

Abstract

This disclosure describes a low cost control architecture for implementation of the Gonzalez-Liang triangle shading algorithm. The Gonzalez-Liang algorithm requires a great deal of area in a special purpose hardware implementation. Many values are generated, and must be stored in registers or register files to preserve the advantages in performance sought in using dedicated hardware. Also, the generation of decodes or addresses for the registers or register files can be expensive in terms of the PLA or random logic complexity.

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Gonzales-Liang Control Architecture for a Graphics Processor

      This disclosure describes a low cost control architecture for
implementation of the Gonzalez-Liang triangle shading algorithm.  The
Gonzalez-Liang algorithm requires a great deal of area in a special
purpose hardware implementation.  Many values are generated, and must
be stored in registers or register files to preserve the advantages
in performance sought in using dedicated hardware.  Also, the
generation of decodes or addresses for the registers or register
files can be expensive in terms of the PLA or random logic
complexity.

      This disclosure describes methods that minimize the PLA, random
logic, or processor microcode necessary for implementing
Gonzalez-Liang by taking advantage of clever register file storage
allocation, efficient partitioning of function among control modules,
parallel execution, re-use of control modules for many similar tasks
with minimum added logic, flexible startup of modules for different
streams of execution, dynamic scheduling of division tasks with
minimum overhead, and general robustness.

      A datapath for Gonzalez-Liang triangle shading, an example of
which is shown in Fig. 1, consists of the following major components:

Vertex Register File   - Buffers triangle vertices from the host
                         processor, allows stack manipulation for
                         polygon and mesh rendering.

Cofactor Generator     - Performs the plane equation solution
                         calculations.

Division Stage         - Performs fast integer divisions (20 in all)
                         to complete setup calculations.

Shading Parameter
Buffers                - Provide intermediate storage for Cofactor
and
                         division tasks, and ping-pong queuing for
                         passing  parameters to the interpolation
                         stage.

Vertex Generation
Subsystem              - Operates in parallel with shading setup and
                         shading systems to provide screen address
                         information.

Shading Interpolation
Subsystem              - Provides final per-pixel color and depth
                         information for display.

      The shaded boxes in Fig. 1 depict the control modules used at
sequential or concurrent segments of algorithm execution.  Fig. 2
shows the modules in more detail.

SETUP MANAGER - Calls the modules controlling the setup portion of
the datapath.  Can use several execution sequences depending upon the
calling parameters.

FILL MANAGER - Calls the modules controlling the fill portion of the
datapath.  Can use several execution ...