Browse Prior Art Database

Methods of Maintaining Shared Memory Coherence with Non-Coherent CPU

IP.com Disclosure Number: IPCOM000105272D
Original Publication Date: 1993-Jul-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Hardell Jr, WR: AUTHOR [+2]

Abstract

Described are methods for maintaining cache coherent shared memory with CPUs that were not designed with MP coherence instructions or functions. This requires a combination of external logic and software protocol.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Methods of Maintaining Shared Memory Coherence with Non-Coherent CPU

      Described are methods for maintaining cache coherent shared
memory with CPUs that were not designed with MP coherence
instructions or functions.  This requires a combination of external
logic and software protocol.

      This discussion is directed at the IBM RISC System 6000* CPUs
that have L1 Data and Instruction caches.  The CPU has Flush,
Invalidate, and Sync (Data Cache Sync:  DCS and Instruction Cache
Sync:  ICS) instructions.  However, the CPU is unable to snoop a bus
or take a flush/invalidate command from an external source.

      The method used to maintain shared memory coherence requires
both hardware and software.  This system needs an atomic complex that
can be used to acquire/release locks and signal other processors.
When one CPU wants to put data in shared memory for another CPU to
use, the first CPU will write the data and then tell the second CPU
(through the atomics) that the data is in shared memory.  The
following steps might be used to put the data in shared memory and
tell the second CPU:

1.  CPU-1 does a store to a shared address (this puts the data in the
    L1 cache).
2.  CPU-1 executes a flush instruction (this moves data from cache to
    shared memory).
3.  CPU-1 tells CPU-2 that the data is in shared memory (through the
    atomics).
4.  CPU-2 reads the data from shared memory.

      However, this does not guarantee that CPU-2 gets the correct
data.  First, the atomic op could execute before the flush is
complete.  Second, CPU-2s read could execute before the flush is
complete.

      To prevent the read from occurring before the store to share...