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Circuitry for Detecting Simultaneous Events in N Independent or Parallel Digital Systems

IP.com Disclosure Number: IPCOM000105277D
Original Publication Date: 1993-Jul-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 73K

Publishing Venue

IBM

Related People

Hennet, PP: AUTHOR [+3]

Abstract

Disclosed is circuitry to allow a sequential memory measurement instrument to determine if n independently addressed memories are in synchronization.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 41% of the total text.

Circuitry for Detecting Simultaneous Events in N Independent or Parallel Digital Systems

      Disclosed is circuitry to allow a sequential memory measurement
instrument to determine if n independently addressed memories are in
synchronization.

      A sequential memory system is built out of n independent 8 bit
memory cards.  The addressing for each memory card is independent.
This means that each card has a separate address counter that is
incremented by one for each new 8 bit entry that is stored on the
card.  Upon filling all n memory cards, it is important to know if
the independent address counters stayed synchronized for the entire
data capture.

      The problem is solved by developing a signal from each
independent memory card that signifies when each memory card
generated a specific memory address.  In this example the specific
address will be the last address generated by each sequential memory.
This 'Completion' signal is detected in such a way as to determine
that it occurred on the same cycle in each independent memory.  This
unique circuitry is modular,  made of slow speed devices but able to
detect that the memories are synchronized within a one half cycle
time interval.

      Fig. 1 describes the circuitry used to make this decision for
exact synchronization of each memory card in a four card memory
system.  Each memory card produces a negative going signal when the
'Completion' address is reached.  These four independent signals are
delayed 1/2 cycles, inverted, and used to clock the 'Completion'
signal of the following memory card into a 'D' latch.  This latching
is performed in a round robin fashion so that the last card latches
the first card.  This circuitry is easily expandable to any number of
independent memory cards because of this simple relationship between
each pair of cards.  If any one of the four(n) memory cards does not
complete on the same cycle, then the latches will not contain all
minus levels.  At the end of any memory trace, the 'NOR' block output
will be a plus level if all four memory cards ended on the same
cycle.  This signal is label '+Successful'.

      Fig. 2 shows an example of a failure to stay synchronized.
Memory card 4 completed one cycle late.  If all four memory cards
complete at the same time then the delayed and inverted clock signals
will latch minus levels into all succeeding latches.  In this example
card 3 will latch a plus level in latch 4.  If any one or more of the
inputs to the 'NOR' gate are plus then the output of the 'NOR' will
be minus or indicate an addressing error has occurred.  This signal
is labelled '-Error'.

8 Bit Memory                ---------
  Cards                     | Dly   |
                ------------>  &    |
---------       |           | Inv   |       ---------
|       |       |           |       |------->C  ...