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Automated Determination of Isolation Test Opportunities in Resistive Termination Sub-Circuits

IP.com Disclosure Number: IPCOM000105292D
Original Publication Date: 1993-Jul-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 6 page(s) / 186K

Publishing Venue

IBM

Related People

Deitz, KG: AUTHOR

Abstract

Automated Determination of Isolation Test Opportunities in Resistive Termination Sub-Circuits, is a test generation algorithm which identifies the non-redundant cases where unwanted DC cross-coupling can occur in R-PACKS. This unwanted condition is difficult to debug, when not tested for explicitly, and is usually found at the system level during system test, when the circuits are running full speed.

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Automated Determination of Isolation Test Opportunities in Resistive Termination Sub-Circuits

      Automated Determination of Isolation Test Opportunities in
Resistive Termination Sub-Circuits, is a test generation algorithm
which identifies the non-redundant cases where unwanted DC
cross-coupling can occur in R-PACKS.  This unwanted condition is
difficult to debug, when not tested for explicitly, and is usually
found at the system level during system test, when the circuits are
running full speed.

      The intent of this method is to identify all the conditions
where this AC fault can occur and include these cases with the real
tests for the real components within the terminator.  The testing is
performed using inexpensive DC measurements.

      An in-circuit tester is the ideal vehicle for such testing,
since it in it's ideal form, it has one test point per net and allows
many parametric tests to be executed on a given net, or between nets.
The in-circuit tester's Automatic Test Generation software is
intended to determine how the tester hardware and software can be
employed to perform the test.  This disclosure's algorithm is
intended to define which tests can and should be done, similar to
what a human Test Engineer must do when developing a card test.

      Isolation is assured when there are no current paths inside the
device which are less than 2 orders of magnitude greater in
resistance value than the largest resistance value inside the device.
Isolation measurements can be done even in parallel circuit
situations, by employing an industry standard technique known as
"guarding".  The nets which isolation is to be measured on are
connected to a constant voltage source and the inverting input of a
current to voltage converter op-amp.  The parallel errors are
nullified by connecting the non-inverting input of the same op-amp to
a net in the parallel path.  The voltage at the output of the op-amp
is now proportional to the isolation resistance measured, and this
voltage is digitized and converted to resistance based on the
constant voltage stimulus.

      This method of identifying DC isolation faults, can find
process problems within the R-PACK, and can even find dendritic
growth.  Typically, dendritic growths develop after a few seconds of
bias application under the correct conditions.  If the test models
created by this method were run against the potentially failing card,
the card could have it's failing component and sub-circuit pointed to
directly by the diagnostics (also generated), and replaced before the
card becomes a difficult to diagnose, expensive system level fail.
The basic low-level algorithm consists of three parts:

1.  R-Pack description parameter parser.
2.  Description table generation and cross checking with reduction.
3.  Formatting of output.  (Output format can be adapted to nearly
    any in-circuit tester manufacturer's test description formats.)

The high-level algorithm...