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Using the Template and In-Line Indicator to Sequence Prefetching

IP.com Disclosure Number: IPCOM000105294D
Original Publication Date: 1993-Jul-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 142K

Publishing Venue

IBM

Related People

Pershing, J: AUTHOR [+2]

Abstract

A cache line comprised of program instructions either sets its own GPR's or uses the GPR's that have been recently set by a prior set of instructions. The ordering of I X D -> D prefetching can use the recency of token setting within the TEMPLATE to order those prefetches that are not inherently self ordered.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 42% of the total text.

Using the Template and In-Line Indicator to Sequence Prefetching

      A cache line comprised of program instructions either sets its
own GPR's or uses the GPR's that have been recently set by a prior
set of instructions.  The ordering of I X D -> D prefetching can use
the recency of token setting within the TEMPLATE to order those
prefetches that are not inherently self ordered.

      The basic mechanism of address generation that has been used to
identify certain D-LINE prefetching opportunities is that the LOAD of
a register is a preliminary step to the generation of an address.  A
processor mechanism called a GLT provides a critical aspect of the
prefetching information.

GLT - Consider the GPR LOCATION TABLE (GLT) which for each of the 15
GPR that can be used for Address Generation (AGEN) contains, if
valid, the address from which the current contents of the GPR was
LOADED.  Entries within this GLT are invalidated by any instruction
that modifies the value of the GPR associated with the entry.  The
entry in the GLT is made at the time of the AGEN operation of the
LOAD instruction which places the value from memory at the location
specified by entry into the associated GPR.  Thus LOAD operations
invalidate the GLT entry but not until it is determined that the LOAD
has not caused a D-CACHE MISS.  In this context the LM is considered
a series of LOAD instructions and the ADDRESSES inserted in the GLT
are the addresses of the 4-BYTE WORDS from which the registers are
loaded.  If the source register of a LR instruction has a valid entry
in the GLT then the entry within the GLT that corresponds to the sink
register is updated appropriately.

      An extension of the GLT involves an IN_LINE_INDICATOR (ILI) bit
that is set whenever a GPR is loaded in the manner described above
and is reset whenever the INSTRUCTION COUNTER (IC) enters a new-line.
Entries that are made in the D-LINE prefetching table are accompanied
by the ILI bit associated with the register used to form the address
so as to indicate whether the setting of this register was within the
line for which the prefetch command has been set, or the register was
set prior to the entry into the line.  Clearly the time-sequence
ordering of a D-LINE prefetch should give a priority to those
commands designated as having their registers set prior to line
entry.

      A second component of the information available to the
prefetching mechanism derives from the TEMPLATE and the recency of
the reference to TOKENS.  The TEMPLATE mechanism associates ADDRESSES
with TOKENS.

o   REFERENCE - The TEMPLATE can be referenced when accessed by TOKEN
    to derive the associated ADDRESS when the TOKEN is used to
    designate D sub LOC-source.

o   UPDATE - The TEMPLATE can be updated when accessed by TOKEN to
    insert a new ADDRESS when the TOKEN is used to designate D sub
    LOC-sink.

o   ASSOCIATE - The TEMPLATE can be accessed by ADDRESS to associate
   ...