Browse Prior Art Database

Multi-Scan Array Built-In, Self-Test with Result/Fail Bits

IP.com Disclosure Number: IPCOM000105297D
Original Publication Date: 1993-Jul-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Akrout, C: AUTHOR [+3]

Abstract

At present, the Array Built-In, Self-Test (ABIST) results are based on "result" bits stored in latches which indicate if the SRAM under test is good or fail. The decision is made at the tester level. In the case where redundancy lines are implemented in the SRAM, a specific bit indicates if the memory is repairable and the FAIL ADDRESS REGISTERS indicates the word or bit line addresses to be repaired.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Multi-Scan Array Built-In, Self-Test with Result/Fail Bits

      At present, the Array Built-In, Self-Test (ABIST) results are
based on "result" bits stored in latches which indicate if the SRAM
under test is good or fail.  The decision is made at the tester
level.  In the case where redundancy lines are implemented in the
SRAM, a specific bit indicates if the memory is repairable and the
FAIL ADDRESS REGISTERS indicates the word or bit line addresses to be
repaired.

      In an ABIST with multiple scans the "result" bits (RESULT and
FAIL) now contain only the fail results of a single SWEEP (A SWEEP is
considered to have occured when the ABIST has tested all addresses
(from the minimum address to the maximum address)), and these
intermediate values need to be saved at the tester level.  A new step
in the test manufacturing process is required to post-process these
values, and to determine by software program the status (PASS, FAIL,
REPAIRABLE) of the memory under test.  The present dislosures
addresses this weakness, and alleviates the need for tester level
post processing.

      The proposal consists in the implementation in the ABIST with
multiple scans, of a mechanism to save the intermediary results as
described above.

      As illustrated in the figure, the apparatus consists of
incorporating a L3 latch (non-scannable latch) on the RESULT bits
combined with a NOOP signal generated by the ABIST logic.  By
including a non-scannable latch after the L1/L2 (LSSD scannable
latch) a tester level post-...