Browse Prior Art Database

Imprecise Residence Recording without Replacement Update for Multiprocessor Caches

IP.com Disclosure Number: IPCOM000105301D
Original Publication Date: 1993-Jul-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 79K

Publishing Venue

IBM

Related People

Liu, L: AUTHOR

Abstract

Precise cache residence recording requires update of replacement activities. Such replacement report may be simply discarded with pessimistic residence information maintained.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Imprecise Residence Recording without Replacement Update for Multiprocessor Caches

      Precise cache residence recording requires update of
replacement activities.  Such replacement report may be simply
discarded with pessimistic residence information maintained.

      It is a well-known method to utilize directories to keep track
of cache residence information in multiprocessor cache systems.  For
instance, a central directory (e.g., for 2nd level cache, main
memory, or just a separate directory) may be used to keep track of
cache line usages.  A typical technique is to use a bit-vector (1-bit
per cache) per line entry of D for the indication of which caches
have copies of the line.  A major benefit of such information is to
avoid unnecessary XI-invalidates (e.g., when a line is shared by
multiple caches and is modified by a processor or I/O channel).  In
conventional proposals such residence information is maintained
precisely.  That, however, requires the update of residence tags at D
when lines are replaced from caches.  For instance, when a cache
needs to make room for a new line L by replacing an old line L', D
needs to be informed of the replacement of L' (in addition to the
line fetch for L).  Also, in many designs (e.g., when D is a
directory much larger than processor caches), L and L' tend to fall
into different congruence classes of D.  As a result, additional
directory cycle is required for D to update the replacement
information for L'.

      It was observed that a line been modified by a processor tend
to be modified by a processor in the not very far past.  Furthermore,
when a channel modifies a memory line, the line tend not to be
recently accessed by any of the caches.  As a result, precisely
maintaining cache residence information with complexity of
replacement updates may not provide significant benefit in many
designs.  The replacement update actions may simply be eliminated.

      The invention is now illustrated with a simple example design
modification to conventional approaches.  Consider a multiprocessor
systems in which each processor has its private cache.  A shared
directory D is assumed for the recording of residence information for
the caches.  Each line entry has a RES-tag of...