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Scheduling Cache Bus during a Miss

IP.com Disclosure Number: IPCOM000105308D
Original Publication Date: 1993-Jul-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 105K

Publishing Venue

IBM

Related People

Rechtschaffen, R: AUTHOR

Abstract

The implementation mechanisms of a partial write-back between two WI levels of a memory hierarchy that are involved in scheduling the activity of the cache bus that affords the maximum flexibility of using: a line buffer, a cast-out buffer, and a cache, during a miss is disclosed. The role played by the partial write back is emphasized.

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Scheduling Cache Bus during a Miss

      The implementation mechanisms of a partial write-back between
two WI levels of a memory hierarchy that are involved in scheduling
the activity of the cache bus that affords the maximum flexibility of
using: a line buffer, a cast-out buffer, and a cache, during a miss
is disclosed.  The role played by the partial write back is
emphasized.

      Summary statistics from processor organizations suggest that as
the level of multiprocessing increases an advantage should be taken
of the Write-In L1-Level.  Traffic can further be decreased using a
partial write back capability.  The traffic of stores to the memory
hierarchy can be reduced by 50% with the use of WI-L1 CACHES in the
hierarchy.

INHERENT ADVANTAGES OF WTWAX - A WTWAX cache management protocol is
defined as:

o   all stores are written through the L1 cache to the L2 (WT),
o   all lines that are stored into by the processors must be
    allocated (WA - WRITE ALLOCATE), and
o   all lines written into must be held exclusively (X).

      The absence of a cast out requirement at the point of a miss
allows the processor to perform concurrent accesses to the cache and
to the line as it is being brought into a LINE BUFFER (LB) using
valid bits.  The arrival of the targeted DW to the line buffer
provides for the continuation of processing until a new miss occurs
or an access to a part of the "missed" line occurs prior to its being
placed in the LB and made valid.  Such a LB has a concurrent
READ/WRITE capability in that it can receive a DW from memory while
it is responding to an access request from the processor.

      The relevance of the LB to the WI cache management protocol
concerns the timing of the putaway of the LB during the latency time
of the next miss if the line being replaced has been modified and
needs to be cast-out.

      Sequence of Events In A Miss - Consider a L1-CACHE made up of
128B lines and equipped with a QW bus.  It takes 8 cycles to transfer
the line into the cache.  If the latency time of the L2-CACHE, the
time to first data back to the LB is 8 cycles, the LB can be cleared
of the previous miss during the latency time of the L2 in a a system
without cast-outs e.g. WTWAX.  For a WI L1-CACHE the use of partial
write-backs in a WI/WI memory hierarchy provides for an opportunity
to coordinate all elements of the traffic involved:

o   Partial write back to the cast out buffer (COB)
o   Clearing of the line buffer into the cashe slot assigned
o   Filling the line buffer from the L2 following the Latency
o   Allowing access from the processor following L2 Letency to both
    the old miss and the new miss.
using the information maintained by the cache as to which QWs were
modified within the line to be cast-out and the QW-within-line
position of the target of the miss.

Fundamental Concept

      The fundamental concept in such a systems involves the total
capacity of the { L1...