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Fast-Switch and Sense Array Data Circuit

IP.com Disclosure Number: IPCOM000105315D
Original Publication Date: 1993-Jul-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 87K

Publishing Venue

IBM

Related People

Bredin, F: AUTHOR [+2]

Abstract

This Large Byte Sense Amplifier (LBSA) circuit is used for selecting of one out of "n" information coming from any large bitline group belonging either to RAM or ROM array matrix. Together with a single ended sense amplifier, it forms a complete low capacitance bitswitch scheme with a very high electrical performance. A conventional arrangement such as a large pass gate device multiplexor combined with a sense amplifier shows a very slow-moving sensing operation, because too many pass gate devices give a too big output capacitance. A too-large multiplexor also causes capacitive coupling, which can generate false data information. So it is necessary to minimize the connection line (CL), to reduce the capacitance of the output common node (Ccl) and to improve the delay accross the multiplexor.

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This is the abbreviated version, containing approximately 52% of the total text.

Fast-Switch and Sense Array Data Circuit

      This Large Byte Sense Amplifier (LBSA) circuit is used for
selecting of one out of "n" information coming from any large bitline
group belonging either to RAM or ROM array matrix.  Together with a
single ended sense amplifier, it forms a complete low capacitance
bitswitch scheme with a very high electrical performance.  A
conventional arrangement such as a large pass gate device multiplexor
combined with a sense amplifier shows a very slow-moving sensing
operation, because too many pass gate devices give a too big output
capacitance.  A too-large multiplexor also causes capacitive
coupling, which can generate false data information.  So it is
necessary to minimize the connection line (CL), to reduce the
capacitance of the output common node (Ccl) and to improve the delay
accross the multiplexor.

      The novel arrangement consists to assemble some elementary 2:1
multi plexors (to form a large byte multiplexor) which already
includes one first sense amplifier device, and complete the sense
operation by a second sense amplifier circuit.

      Now referring to Fig. 1, the multiplexor circuit consists of a
pair of P-MOS devices TM0 and TM1.  Both drains of TM0 and TM1 are
connected together to the CL common wire.  The Ccl' common line
capacitance is now reduced when compared to the equivalent
capacitance in the conventional arrangement mentioned above.  Sources
of TM0 and TM1 are respectively connected to the bitline 0 (BL0) and
to bitline 1 (BL1).  BL0 or BL1 are selected by activating  BSW0 or
BSW1.  The CL common wire is also the input of the first sense
amplifier device (TXS0).

      In restore mode, the CL common wire is connected to VDD through
the TRST device turned on (RST signal is in low state).

      In read mode,...