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Sacrificial Oxide Process during Aluminum Polishing

IP.com Disclosure Number: IPCOM000105324D
Original Publication Date: 1993-Jul-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Fournier, B: AUTHOR

Abstract

In the VLSI semiconductor manufacturing, different methods are used to planarize the metallurgy/insulator levels for circuit personalization.

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Sacrificial Oxide Process during Aluminum Polishing

      In the VLSI semiconductor manufacturing, different methods are
used to planarize the metallurgy/insulator levels for circuit
personalization.

      One of the recent methods use to planarize the insulator layers
is by "CHEM-MECH" polishing.  Connections between the different
metallurgy levels, are achieved as standard by etching via-holes
through these insulator layers, and filling the same through aluminum
evaporation.

      After filling, a new polishing step is performed to eliminate
the aluminum coating that is deposited on the whole substrate.  A
nitride layer is used as an etch-stop layer for the aluminum
polishing.

      The problem that is often met with this method consists in the
formation of aluminum islets or puddles of poor thickness.  These
"pud dles" are the consequence of topological depressions because it
is not possible to have a perfectly plane surface.  During the
realization of the superior level of circuit, these "puddles" risk to
join two lines or lands of inter-connection scheme causing thereby a
potential electrical defect.

      The solution proposed herein below aims to eliminate this
problem.  It consists of depositing an oxide coating above the
nitride etch-stop layer.  This oxide coating will smooth all topology
depressions to leave a perfelectly planar surface.  It will
subsequently be removed during the aluminum polishing step.  The
aluminum islets or pu...