Browse Prior Art Database

Graphics Floating Point Engine Modular Testing and Fault Isolation

IP.com Disclosure Number: IPCOM000105326D
Original Publication Date: 1993-Jul-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 98K

Publishing Venue

IBM

Related People

Jaber, T: AUTHOR [+3]

Abstract

This technical disclosure describes test logic and fault isolation features for implementation on a graphics floating point engine chip. The graphics floating point engine chip is a specialized graphics processor chip with 3 floating point and 2 fixed point execution units. These special test and fault isolation features were intended to simplify the test diagnostics software normally used by manufacturing test in fault diagnosis and isolation. They were also intended to simplify fault isolation during chip bring-up, debug and Built-In Self-Test (BIST) operation. This technique also allows us to salvage partially functional graphics floating point engine chips with various configurations of floating point and fixed point execu-tion units.

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Graphics Floating Point Engine Modular Testing and Fault Isolation

      This technical disclosure describes test logic and fault
isolation features for implementation on a graphics floating point
engine chip.  The graphics floating point engine chip is a
specialized graphics processor chip with 3 floating point and 2 fixed
point execution units.  These special test and fault isolation
features were intended to simplify the test diagnostics software
normally used by manufacturing test in fault diagnosis and isolation.
They were also intended to simplify fault isolation during chip
bring-up, debug and Built-In Self-Test (BIST) operation.  This
technique also allows us to salvage partially functional graphics
floating point engine chips with various configurations of floating
point and fixed point execu-tion units.

      The graphics floating point engine chip is a specialized
graphics processor with multiple execution units.  Three floating
point and two fixed point execution units.  These various execution
units are all completely independent from each other and have no
logical interaction even when fully operational.  To take advantage
of this functional characteristics, it was necessary that this
independency between the various execution units be preserved when
test logic is implemented on the chip.  Based on that, each execution
unit was assigned a unique scan string that was fully contained
within a particular execution unit logic.  For exam-ple, floating
point execution unit 0 was assigned scan string 0, floating point
execution unit 1 was assigned scan string 1 and so on (Fig. 1).

      This scan string assignment made it a lot easier to isolate a
faulty execution unit.  All that was required for this isola-tion is
for the test engineer to turn off the tester 'measure' commands on
that particular execution unit scan string and watch for any tester
fail signals.  If a previously failing chip now passes the test data
after turning off the tester measure commands on scan...