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Link Condition Test in Crosspoint-Switched Parallel Processor Systems

IP.com Disclosure Number: IPCOM000105366D
Original Publication Date: 1993-Jul-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 73K

Publishing Venue

IBM

Related People

Blum, A: AUTHOR [+3]

Abstract

This article describes a link condition test in crosspoint-switched parallel processor systems.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Link Condition Test in Crosspoint-Switched Parallel Processor Systems

      This article describes a link condition test in
crosspoint-switched parallel processor systems.

      In a parallel processing environment using circuit switching
means, such as a crosspoint switch, a well-defined starting point for
data/information transmission is required for the communication
between the linked processors.

      Normally, the addressed unit sends a special data pattern via
the switch to signal the initiating unit to recognize a successfully
switched connection and also its "ready to receive" status.  This
means an additional effort for data/control lines and a higher
complexity of the logic circuits for the switch adapter chip.

      At the end of communication, the switch connection is
terminated by a disconnect command sent by one of the two units.
Connect/disconnect commands are executed by the matrix controller
function/chip.  For system reliability, this should be checked to
avoid satellite hang and error situations.

      The proposed link condition test ensures the two described
functions most effectively.

      The figure shows the logic parts of such a parallel processing
en vironment.  It is assumed that unit A intends to exchange informa
tion/data with unit B and that the switch attachment of unit A sends
a connect command to the matrix controller with the addresses of A
and B by using the bus to which all switch adapters are connected.
Via a special bus, the matrix controller then tells the switch to
build up the A/B connection.

      "Ready to receive" signalling is effected by selecting the
location of the pull-up resistor and the active level of two...