Browse Prior Art Database

Connecting CPUs that were Designed to be Masters in an MP Configuration

IP.com Disclosure Number: IPCOM000105367D
Original Publication Date: 1993-Jul-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 73K

Publishing Venue

IBM

Related People

Hardell Jr, WR: AUTHOR

Abstract

This disclosure describes a means for connecting CPUs that were designed to be masters of the memory bus in a Multi-Processor configuration to a shared global memory sub-system.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Connecting CPUs that were Designed to be Masters in an MP Configuration

      This disclosure describes a means for connecting CPUs that were
designed to be masters of the memory bus in a Multi-Processor
configuration to a shared global memory sub-system.

      The IBM RISC System 6000 CPUs were design to be the master on
the memory bus.  The CPU could put up to 2 requests on the memory bus
at any time.  When one of the 2 requests was done, the CPU could put
another request on the bus.  The memory cards were designed with the
requirement that they must be able to handle 2 queued requests.

      The DATA_VAL and DATA_RDY were the signals that indicated that
there was valid write and read data on the bus, respectively.  The
DATA_VAL and DATA_RDY are active 2 cycles before data is actually on
the bus (this gives the receiving device time to prepare for the
data).  The normal CPU mode for write data is that CPU can send out
the DATA_VAL (followed by the data) at the same time as the request
is sent out.  The memory cards were designed to be able to take at
least 4 transfers of data even if the DRAMs are busy (e.g.,
refreshing).  Therefore, the memory cards have at least a 4 deep
write data buffer.  If the memory card is not going to be able to
handle additional groups of 4 transfers, then the memory card will
activate a DATA_HLD signal to tell the CPU not to send additional
data after the present group of 4 is complete.  Below are two methods
of connecting these CPUs to a shared memory sub-system.

      The first method to connect the CPUs to global memory through a
switch queues the requests in the switch, but passes the data,
DATA_VAL, DATA_RDY, and DATA_HLD through the switch with 0 cycles of
delay.  This method has the highest system performance as long as the
data and data controls can make it from source to destination in 1
cycle.  If the cycle ti...