Browse Prior Art Database

Skew-Reduction Method in VLSI Design

IP.com Disclosure Number: IPCOM000105376D
Original Publication Date: 1993-Jul-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Eguchi, S: AUTHOR

Abstract

Disclosed is a skew reduction method in VLSI design which includes: a) interchangeable layout cells with the same function but with the different delay characteristics; b) placement and routing using the cells with average delay characteristics; and c) exchange of the cells by the results of post-layout timing analysis for skew reduction.

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Skew-Reduction Method in VLSI Design

      Disclosed is a skew reduction method in VLSI design which
includes: a) interchangeable layout cells with the same function but
with the different delay characteristics; b) placement and routing
using the cells with average delay characteristics; and c) exchange
of the cells by the results of post-layout timing analysis for skew
reduction.

      A variance in signal propagation (skew) is one of the major
obstacles in achieving the high speed VLSI design, and with the
advent of synchronous design in recent large scale integration, a
skew reduction of clock signals is of the most interested.

      The figure shows a pictorial example of Flip-Flop (F/F) cells
A,B and C which occupy the same area in layout with the identical
terminal pinouts and are interchangeable without redoing the
placement and routing.

      Cell B, being the average cell, has the clock delay
characteristic of t in relation to data input.  Cell B is used in the
logic design.  Cell A has less clock delay than cell B by t, and cell
C has more clock delay than cell B by t.  Cells A and C are the
replacement cells to cell B for clock skew reduction.

      Delay-value of t is best determined from the level of skew
controls achievable by the layout software in use with existing skew
reduction techniques such as:

o   Clock tree generation with balanced loading
o   Optimized clock buffer placement
o   Prioritized clock signal routing with w...