Browse Prior Art Database

Technique for Controlling Chip Power-On Reset

IP.com Disclosure Number: IPCOM000105392D
Original Publication Date: 1993-Jul-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 107K

Publishing Venue

IBM

Related People

Jaber, T: AUTHOR

Abstract

Power-On Reset control for the RISC System/6000* system as well as follow-on systems was achieved by dedicating an Intel chip, commonly referred to as OCS (On Card Sequencer), to provide the proper POR control. Because of card space limitation, card cost as well as manpower and scheduling requirements, it was necessary to do away with the OCS chip and built the POR control as an integral part of the on-chip logic. This disclosure describes a technique that allows the chip POR control logic to be integrated on the application chip itself

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Technique for Controlling Chip Power-On Reset

      Power-On Reset control for the RISC System/6000* system as well
as follow-on systems was achieved by dedicating an Intel chip,
commonly referred to as OCS (On Card Sequencer), to provide the
proper POR control.  Because of card space limitation, card cost as
well as manpower and scheduling requirements, it was necessary to do
away with the OCS chip and built the POR control as an integral part
of the on-chip logic.  This disclosure describes a technique that
allows the chip POR control logic to be integrated on the application
chip itself

      The RISC System/6000 system included an Intel 8051 controller
chip for the purpose of controlling the POR function of the processor
card.  The Intel chip, referred to commonly as the OCS, communicated
to a Common ON-chip Processor (COP) that existed on every chip of the
Central Electronics complex (CEC).  This communication took place
over a 4 bit wide testability bus according to a predefined bus
protocol.  POR and other instructions would be sent serially over the
testability bus to the COPs on every chip.  A particular function is
normally achieved by a series of COP instructions issued by the OCS.
A typical POR function would look something like the following:

          1- RESET COP/CHIP         /*RESET COP LOGIC AND FLUCH CHIP
SCAN STRING
          */
          2- EN FREEZE....(0023)    /*COP TAKES CONTROL OF CHIP
CLOCKS */
          3- LOAD COPSS...(0016)    /*LOAD COP WITH ARRAY
INITIALIZATION DA
          4- EN AI.........(0019)   /*ENABLE ARRAY INITIALIZATION OP
*/
          5- DIS FREEZE.....(0024)  /*COP RELINQUISHES CONTROL OF
CHIP CLOCKS */

     The above function would initialize the chip arrays to a
predefined state.  It includes five instructions that need to be
issued by the OCS serially over the COP bus.  The complete POR
function could include additional instruction sequences.

      This disclosure describes a Finite State Machine (FSM) that was
designed to provide the same control that the OCS initially provided
for the RISC System/6000 system.  The only function that this FSM
does not support is Built-In Self-Test at POR time.  This was due to
the excessive data volume required to store the PRPG seed and MISR
signatures.  The FSM is a 3 bit sequential logic that was designed
for a special Graphics Processor called the GFPE chip.  The same FSM
was to be used also by another Graphics chip called ARC...