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Browse Prior Art Database

Offloading Synchronization at 2nd Level

IP.com Disclosure Number: IPCOM000105400D
Original Publication Date: 1993-Jul-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 186K

Publishing Venue

IBM

Related People

Liu, L: AUTHOR

Abstract

Effective synchronization support for software programs is a fundamental requirement in modern processors. Normally an architecture supports certain interlock instructions for this purpose. Examples in 370* architecture are Test-and-Set (TS) and Compare-and-Swap (CS). When such instructions are executed certain serializations are required by the architecture. In 3081 type processor designs, exclusive (EX) states are used on cache lines holding the operands for such instructions in order to achieve the architecture serialization properly. However, since such instructions are often used for relatively sharing intensive purposes like locking, the implementation with EX states often results in many cache cross-interrogate (XI) activities.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 28% of the total text.

Offloading Synchronization at 2nd Level

      Effective synchronization support for software programs is a
fundamental requirement in modern processors.  Normally an
architecture supports certain interlock instructions for this
purpose.  Examples in 370* architecture are Test-and-Set (TS) and
Compare-and-Swap (CS).  When such instructions are executed certain
serializations are required by the architecture.  In 3081 type
processor designs, exclusive (EX) states are used on cache lines
holding the operands for such instructions in order to achieve the
architecture serialization properly.  However, since such
instructions are often used for relatively sharing intensive purposes
like locking, the implementation with EX states often results in many
cache cross-interrogate (XI) activities.

      In certain systems some of such synchronization functions are
architected to execute at storage.  An example is the implementation
of Fetch&OP instructions in RP3 systems.  In such a system the
operand words are allocated in non-cacheable storage areas.  Also, in
370 processors, there have been implementations that allow certain
operations to bypass the cache.  One such example is for MVCL type
instructions.  Integral page movements are offloaded from the cache
to main storage, with appropriate cache invalidates.

      This disclosure provides a scheme in which certain interlock
instructions may be implemented in a way that most executions are
offloaded to storage controller without assuming non-cacheable
storage architecture.  The idea is to offload such executions by
detecting the dynamic status for certain instructions.

      The following is an illustration of the invention with an
implementation of CS instruction in a 3081 like system environment.
Some extensions of the scheme will be discussed later.  Consider a
3081 type MP system [*], in which a Storage Control Element (SCE)
controls the storage accesses for multiple processors and the I/O
channels (See the Figure).  The SCE supports EX status for individual
lines in each cache in the processor Buffer Control Element (BCE).
Each processor BCE maintains a Store-In Cache (SIC).  A cache line at
a cache can be of Read Only (RO) or EX status.  RO lines can only be
fetched from but not stored into the associated processor.  In this
invention it is assumed that the SCE maintains an extra (store-in)
cache SCACHE for operands of CS instructions.  SCACHE, as in other
caches in 370 processors, is transparent to the software programs,
although the system software may be constructed to properly benefit
from a performance point of view.  The SCE guarantees that, when a
line in SCACHE will never be resident in any of the processor caches.
In some sense the lines in SCACHE may be regarded as EX for the SCE
itself.  The SCE implements proper directory for SCACHE.  It also
implements necessary logic and data registers for the execution of CS
instructions.

In 370 architecture...