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Bit String Compare Operations for Image Processing

IP.com Disclosure Number: IPCOM000105414D
Original Publication Date: 1993-Jul-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 105K

Publishing Venue

IBM

Related People

Findley, RL: AUTHOR [+5]

Abstract

Three new instructions have been included to support bit string compare operations for image processing. Each has the ability to perform a compare and write to any condition register field. This allows the compiler to distance the compares from the branch. This capability is essential to a pipelined machine to minimize branch penalties. This is critical to image compression and decompression.

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Bit String Compare Operations for Image Processing

      Three new instructions have been included to support bit string
compare operations for image processing.  Each has the ability to
perform a compare and write to any condition register field.  This
allows the compiler to distance the compares from the branch.  This
capability is essential to a pipelined machine to minimize branch
penalties.  This is critical to image compression and decompression.

      Image processing involves vast amounts of data that is used to
represent the image.  Due to the data intensive nature of images,
considerable effort has been put forth by the computing industry to
create more optimal and innovative data compression techniques.

      While these techniques vary widely, the techniques for data
com- pression and decompression are quite similar.  For instance, bit
string encodings may vary widely, but they can (almost exclusively)
be repre- sented by a series of directed graphs and decision trees.
Thus, the problem reduces to a series of compares and branches.

      Decision graphs are branch intensive.  The sheer number of
compares involved creates a problem for pipelined machines.  This is
because normally the result of each branch is written to the same
condition register.  Thus, each branch must be resolved before the
next compare is performed.  Since no work may be done between these
branches, the branch cycle penalty will balloon.

      Described are three microprocessor instructions which assists
in reducing branch penalties by allowing useful instructions between
compares and branches.  These instructions have the capability to
perform a compare and write the result of the compare to any of the
condition register fields.  This alleviates the dependency of the
branches and successive compares.

      The first two instructions, test bit (tstb) and test bit
immediate (tstbi), perform single bit comparisons and write the
results o...