Browse Prior Art Database

Efficient Method to Compute Reciprocal and Riciprocal Square Root in RISC Processors

IP.com Disclosure Number: IPCOM000105415D
Original Publication Date: 1993-Jul-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 82K

Publishing Venue

IBM

Related People

Baur, M: AUTHOR [+4]

Abstract

Most of the RISC processors are providing reciprocal and reciprocal square root generation in hardware recently. Division hardware is provided if reciprocal is not provided in the instruction set. These operations require a number of cycles to complete and are not very suitable for RISC processors to implement them as single instructions. If they are implemented as single instructions, the processor hardware has to accommodate the variations of multi-cycle operation because most of the other instructions are single cycle operations.

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Efficient Method to Compute Reciprocal and Riciprocal Square Root in RISC Processors

      Most of the RISC processors are providing reciprocal and
reciprocal square root generation in hardware recently.  Division
hardware is provided if reciprocal is not provided in the instruction
set.  These operations require a number of cycles to complete and are
not very suitable for RISC processors to implement them as single
instructions.  If they are implemented as single instructions, the
processor hardware has to accommodate the variations of multi-cycle
operation because most of the other instructions are single cycle
operations.

      There are two ways of implementing these multi-cycle operations
in hardware.  One is to have dedicated hardware for these
instructions different from the pipeline structure so that the
pipeline can still receive other instructions while division or
reciprocal or reciprocal square root operation is in progress.  The
other method is use the pipeline repeatedly to complete the
multi-cycle operation for a number of cycles.  The drawback of the
first method is that it requires extra hardware.  The second method
ties up the floating point unit pipeline for a number of cycles,
stalling further instruction issue until the opera- tion is
completed.  A different method of computing reciprocal and reciprocal
square root can be in superscalar RISC processors.  The method is
very efficient and does not have the drawbacks of the above stated
methods.  It is based on the following three-step method.

The three steps in reciprocal and reciprocal square root generation
are:

      Step 1: Seed generation.  This assumes that there are single
cycle instructions for seed computation.  Two instructions can be
provided to accomplish this step.  For IEEE single precision floating
point format, it is enough to provide a seed of six  bits precision.
Some extra random logic is provided for both reciprocal and
reciprocal square root compu- tation.  These two seed instructions
also use the pipeline of the float- ing point unit and are sin...