Browse Prior Art Database

Bipolar CMOS Transistor Structure with Minimum Topography

IP.com Disclosure Number: IPCOM000105416D
Original Publication Date: 1993-Jul-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 80K

Publishing Venue

IBM

Related People

Sun, Y: AUTHOR

Abstract

Described is a bipolar CMOS (BICMOS) transistor structure and fabrication process designed to provide minimum topography for process integration.

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Bipolar CMOS Transistor Structure with Minimum Topography

      Described is a bipolar CMOS (BICMOS) transistor structure and
fabrication process designed to provide minimum topography for
process integration.

      The BICMOS structure described herein utilizes epitaxial
(epi)/poly co-deposition after the field isolation gives a raised
collector and an extrinsic base contact over the field.  The
structure is designed for bipolar devices as well as the polysilicon
gate for CMOS devices.  Fig. 1 shows a cross sectional view of the
completed BICMOS structure utilizing the co-deposition of the
extrinsic base poly and poly gate.  Fig. 2 shows the cross sectional
view of the structure after the epi/poly co-deposition.  Region 2 is
the polysilicon layer co-deposited at the same time with Region 1 by
means of non-selective epitaxy.  A thin polysilicon layer may be used
to protect the CMOS gate insulator integrity and cover most of the
field so as to ease the surface cleaning process before the epi/poly
co-deposition, as shown in Fig. 3.

      The polysilicon layer over the field and the CMOS area is very
planar and is patterned and etched to define the CMOS gate and the
bipolar device extrinsic base only after the bipolar polysilicon
emitter has been defined and etched.  As a result, there is no
topography and associated rail problems during the BICMOS fabrication
process.

      The structure offers minimum parasitic capacitance and
resistance since the ex...