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Processing Instructions within the L2

IP.com Disclosure Number: IPCOM000105424D
Original Publication Date: 1993-Jul-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 132K

Publishing Venue

IBM

Related People

Rechtschaffen, R: AUTHOR

Abstract

For a class of instructions and a class of short instruction sequences the dominant activity concerns the memory hierarchy.These cases are best handled by processing the instructions at the level within the hierarchy where the operands are located, namely the L2.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 51% of the total text.

Processing Instructions within the L2

      For a class of instructions and a class of short instruction
sequences the dominant activity concerns the memory hierarchy.These
cases are best handled by processing the instructions at the level
within the hierarchy where the operands are located, namely the L2.

      In a situation where most of the data for a given instruction
resides at a certain level of the memory hierarchy a serious question
arises as to the efficacy of moving data to the L1 level in order to
execute the instruction.  It is clear that instructions which are
intensive in their movement of data, or comparison of data, might
well be executed at the level of the hierarchy where the data resides
so as to avoid a series of unnecessary misses and modification of the
cache contents at the L1-CACHE level that merely accomplishes: the
movement of the data, the setting of a register value, and a
condition code.

PROCESSING INSTRUCTIONS WITHIN THE L2 - One would like to broaden the
class of processor functions that are amenable to being processed
within an L2 to those that occur within LOOPS.

Consider the following loop:

   LOOP  L   R1, D1(R1)
         TM  X'FF', D2(R1)
         BE  LOOP

The operand requirements for this loop can be deduced by using a
processor extension that communicates:

o   the location from which the GPR was loaded.
o   the value found of the GPR, and
o   the address of the target of the D-CACHE miss,
on each D-CACHE miss created by this loop to a Miss-Monitoring
Mechanism (MMM) within the L2.  The characteristic pattern of the
information communicated to the MMM allows the operand requirements
of the LOOP to be characterized in terms of the following triad:

                 { PTR.LOCATION ; D2 ; D1 }

      and the recursively use of the transformation:

o   PTR.LOCATION -> PTR.VALUE;
o   PTR.VALUE + D2 -> TEST.BYTE.LOCATION;
o   PTR.VALUE + D1 -> NEXT.PTR.LOCATION.

Only one additional piece of information is required to complete the
execution.  The termination condition of the recursion.  Using the
mask within the TM instruction and the flag within the conditional
branch a determination can be made by the L2 as the manner in which
the LOOP terminates.  L2 EXECUTION ALGORITHM

1.  The L2-CACHE supplies each recursion of execution with the
    TEST.BYTE.VALUE and performs the test which determines if another
    recursion is required.

2.  If the test indicates the recursion should continue the
    NEXT.PTR.LOCATION, NEXT.PTR.VALUE, and NEXT.TEST.BYTE.LOCATION
    are calculated and the NEXT.TEST.BYTE.VALUE is presented to the
    execution phase within the L2.

3.  If the test indicates the recursion should stop the
    NEXT.PTR.VALUE, NEXT.TEST.BYTE.VALUE are presented to the
    processor as if the information was being made available as if
    via the miss process.

4.  The loop execution for the loop terminating input wi...