Browse Prior Art Database

Provision for an Abortee Micro Channel Cycle

IP.com Disclosure Number: IPCOM000105432D
Original Publication Date: 1993-Aug-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 70K

Publishing Venue

IBM

Related People

Aldereguia, A: AUTHOR [+3]

Abstract

Disclosed is a circuit using the address latch enable signal on a Micro Channel* bus to gate the Micro Channel status signals provided as inputs to a device, such as the memory controller, not having the ability to handle an aborted Micro Channel cycle. The device protected in this way does not recognize the occurrence of an aborted cycle, in which a status signal is provided without the address latch enable signal.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Provision for an Abortee Micro Channel Cycle

      Disclosed is a circuit using the address latch enable signal on
a Micro Channel* bus to gate the Micro Channel status signals
provided as inputs to a device, such as the memory controller, not
having the ability to handle an aborted Micro Channel cycle.  The
device protected in this way does not recognize the occurrence of an
aborted cycle, in which a status signal is provided without the
address latch enable signal.

      As shown in the figure, memory controller 10 is provided with
input status signals ZS0_ and ZS1_, which are developed as outputs of
a Programmable Array Logic (PAL) module 12, in accordance with
equations 1) and 2), implemented in this module 12.

      In a normal cycle requiring the operation of memory controller
10, the address supplied as an input thereto is decoded within the
control ler, which responds by sending the MSEL_ signal to PAL module
12, indicating that the planar memory has been selected.  Various
signals are provided to module 12 by the Bus Master circuit
controlling operation of the Micro Channel, including the S0 and S1
Micro Channel status signals and the command signal (CMD_).  Other
signals representing the timing of operations and indicating the type
of cycle taking place are supplied as inputs to PAL module 12,
including the DCONVERT signal indicating a DMA conversion cycle, the

HLDA signal indicating a hold acknowledge condition, ZIORDY
indicating the Micro Channel is ready, an...