Browse Prior Art Database

Address-Translation Patching Mechanism

IP.com Disclosure Number: IPCOM000105436D
Original Publication Date: 1993-Aug-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 159K

Publishing Venue

IBM

Related People

Curran, BW: AUTHOR [+3]

Abstract

This invention permits address translator hardware errors to be easily repaired. Even with extensive simulation translator hardware has been prone to design errors in previous machines. These errors are primarily due to the complexity of the architecture and to the complications of supporting multiple architectures.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 39% of the total text.

Address-Translation Patching Mechanism

      This invention permits address translator hardware errors to be
easily repaired.  Even with extensive simulation translator hardware
has been prone to design errors in previous machines.  These errors
are primarily due to the complexity of the architecture and to the
complications of supporting multiple architectures.

      A mechanism is described whereby hardware sequences the
mainline address translations until a design error is detected.  The
faulty sequence is subsequently 'patched' by milli-code.  In this
manner the invention retains the advantages of both a hardware
translator (performance) and a milli-code translator (flexibility).
The hardware function must still be fixed to regain the performance
advantages of a strictly hardware design.  However, hardware
turnaround time no longer impacts system test which can resume as
soon as the milli-code translation sequence is written.

      To minimize performance degradation the invention permits the
hardware to perform the host translations of a patched guest
translation sequence.  This invention may also allow one to implement
future architectures.  Although system performance would be
substandard, operating system development could take advantage of
early architecturally correct hardware.

      Fig. 1 illustrates the invention hardware.  The translation
lookaside buffer (TLB) and ART lookaside buffer (ALB) miss signals
are intercepted by logic which:

o   steers the translation request to the hardware or milli-code
    based on the state of a patch vector bit
o   selects a non-deleted, non-locked TLB entry for the subsequent
    TLB update operation of a milli-code translation.

      When a patched translation is required for an instruction fetch
or an operand access for an instruction, that instruction is
suppressed, a special program interrupt code (PIC) is presented to
milli-code and exception condition reset is presented to the
hardware.  Upon receiving the special PIC milli-code extracts the
address requiring translation, table origin, and type of translation
from the translator.  When milli-code completes the translation it
returns the resulting real address or segment table origin to the
hardware for the TLB or ALB update, respectively.  The instruction is
then retried.  The two novel aspects of the disclosed invention are
described in further detail:

o   The special milli-code hooks which allow code to take over the
    translation sequence and,
o   TLB entry locking mechanism.

The special milli-code system requests are:
set-patch-vector to initialize the hardware patch register.  Each bit
     of the register corresponds to a specific class of address
     translation sequences.  For example: bits 0,1, and 2 may
correspond
     to ART (Access-Register Translation), native DAT (Dynamic
Address
     Translation), and RRF Guest DAT, respectively.  An exception is
  ...