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Program to Power-Up Logic Using an Early Timing Estimator and for Sizing Devices within Performance and Size Constraints

IP.com Disclosure Number: IPCOM000105443D
Original Publication Date: 1993-Aug-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 4 page(s) / 126K

IBM

Related People

Barreh, JI: AUTHOR [+4]

Abstract

When designing a logic circuit, the designer must match each signal driver to the load that driver sees. This match allows the driver to create quick signal transitions without wasting power and space on an oversized driver. In addition, the delay through a driver generally is a function of its internal delay plus its loading coefficient times the load the driver must control. If the device is grossly oversized, the driver will take longer to drive than it would have if it had the proper sizing due to the larger internal delay. For any one device, a simple minimization of the delay function of the block solves the problem. However, when many drivers must be sized simultaneously, the problem becomes intractable; the total delay equation for the network involves too many variables to simply be minimized.

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Program to Power-Up Logic Using an Early Timing Estimator and for Sizing Devices within Performance and Size Constraints

When designing a logic circuit, the designer must match each
signal driver to the load that driver sees.  This match allows the
driver to create quick signal transitions without wasting power and
space on an oversized driver.  In addition, the delay through a
driver generally is a function of its internal delay plus its loading
coefficient times the load the driver must control.  If the device is
grossly oversized, the driver will take longer to drive than it would
have if it had the proper sizing due to the larger internal delay.
For any one device, a simple minimization of the delay function of
the block solves the problem.  However, when many drivers must be
sized simultaneously, the problem becomes intractable; the total
delay equation for the network involves too many variables to simply
be minimized.

The simple heuristic adopted for solving this problem called
for minimizing the delay through each block in the network.  However,
the implementation of this heuristic ignored the fact that as it
changed the network, it changed the loads the blocks experienced.
This prevented the process from actually minimizing the delay through
each block.  Since the old solution did not take the extra loading
into account, the process had to be run multiple times to get
acceptable results.  Howev- er, running the process took significant
amounts of the designer's time.

The solution involved moving the process of assigning driver
sizes (called powering up or powerup) to an environment where the
changes in the network could easily be reflected in the data used to
assign driver sizes.  If the process could update the data as it
changed the network, then multiple passes would not be required.  The
Design Automated DataBase (DADB) environment was selected for its
ease of use and its ability to access all needed information to
minimize each block's delay.

The process was ported to the DADB environment, the process
minimized the block delays in one pass.  However, in selecting the
minimal block delay, the process selected much larger blocks for
rela- tively insignificant delay reductions.  Some groups of devices
had increased in area up to 25% over the old process.  The
minimization metric was modified to take into account not only the
delay through the block and whether the output signal met its
expected arrival time, but also how much the change in device size