Browse Prior Art Database

Asynchronous Clock-Noise Reduction Technique

IP.com Disclosure Number: IPCOM000105453D
Original Publication Date: 1993-Aug-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Galbraith, RL: AUTHOR [+3]

Abstract

A method to reduce unwanted clock noise from sensitive analog signals is disclosed. Described is a method that reduces interference from a clock during the reading of sensitive analog data.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Asynchronous Clock-Noise Reduction Technique

      A method to reduce unwanted clock noise from sensitive analog
signals is disclosed.  Described is a method that reduces
interference from a clock during the reading of sensitive analog
data.

      Higher data rates in disk drives requires the packaging of the
electronics card(s) to be designed to reduce interference between
digital clocks and the sensitive analog circuitry.  While traditional
techniques of grounding and shielding are the first line of defense,
these methods are limited by the card wiring density, number of power
planes, component density and wiring impedance.  Even with the best
techniques of reducing high speed digital interference, it cannot
totally eliminate unwanted clock interference.

Fig. 1 shows a block diagram of the Partial Response Digital Filter
(PRDF) timing loop.

      The solution is a method that eliminates the asynchronous clock
noise.  Most sample detection systems rely on having a reference
clock on continuously during read and non-read mode conditions.  This
clock is needed to keep the Voltage Controlled Oscillator (VCO)
within range so when read mode occurs, the data can quickly
synchronize to the VCO.  Once the VCO is synchronized with the data
signal, the asynchronous reference clock is not needed.  In idle mode
the VCO is locked to an external reference clock via the 360 degree
phase detector.  With this mode, the analog data signal will contain,
among other things, mostly fundamental and 3rd harmonic noise
coupling...