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Clocking Circuit for Flush L1 Latches in the RISC Single Chip Processor

IP.com Disclosure Number: IPCOM000105480D
Original Publication Date: 1993-Aug-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 80K

Publishing Venue

IBM

Related People

East, RE: AUTHOR [+4]

Abstract

Disclosed is a clocking scheme for flush L1 registers that allow these registers to participate correctly in all operating modes of the chip. In addition, a detailed implementation has been provided as an example.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Clocking Circuit for Flush L1 Latches in the RISC Single Chip Processor

      Disclosed is a clocking scheme for flush L1 registers that
allow these registers to participate correctly in all operating modes
of the chip.  In addition, a detailed implementation has been
provided as an example.

      High test coverage is an important aspect of microprocessor
design.  In addition, the ability for easy access to state
information inside the processors and the ability for processors to
automatically test and reset themselves are becoming more and more
important.  These diverse requirements place additional demands on
the clocking logic of conventional microprocessors.

      The RISC Single Chip (RSC) microprocessor employs a versatile
clocking scheme which allows it to operate in many different modes.
These modes include the following:

1.    Functional Mode
2.    LSSD Mode
3.    POR and Reset Mode
4.    Engineering Support Processor (ESP) Access Mode
5.    Array Self Test (AST) Mode
6.    Array Initialization (AI) Mode
7.    DC Logic Self Test (DCLST) Mode
8.    AC Logic Self Test (ACLST) Mode

      The RSC design point has sections of logic where on-chip arrays
must functionally feed other on-chip arrays.  In general, this
practice is an LSSD rules violation which can be fixed through the
use of either either "flush L1 registers" or "L2* registers".  In the
case of the RSC chip, we chose to use the "flush L1 registers" to fix
this problem.  However, in order for the flush L1 registers to
operate correctly in all modes mentioned above, special clocking
circuitry had to be added.  This disclosure describes the clocking
circuitry.

      The clocking for the flush L1 register must behave in the
following manner for each of the various modes of chip operation:

Functional Mode - The register should simply flush the data through
it.  The clock should simply remain active (high)...