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Interface Circuit for Single-Ended Self-Timing/Resetting

IP.com Disclosure Number: IPCOM000105487D
Original Publication Date: 1993-Aug-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Drake, CE: AUTHOR [+3]

Abstract

A driver circuit is described that complies with the requirements for a ternary, single-ended, self-timed logic interface protocol [*]. A third or "spacer" level, such as VDD/2, between logic 1 and logic 0 levels is introduced to permit detection of a data signal event. The driver output resides at the spacer level whenever the two complementary data inputs to the driver are at the same level. Such a condition occurs during precharge or in the event of abnormal signal conditions. Recognition of the onset of the finish condition provides self-timing information on the same bus as data.

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Interface Circuit for Single-Ended Self-Timing/Resetting

      A driver circuit is described that complies with the
requirements for a ternary, single-ended, self-timed logic interface
protocol [*].  A third or "spacer" level, such as VDD/2, between
logic 1 and logic 0 levels is introduced to permit detection of a
data signal event.  The driver output resides at the spacer level
whenever the two complementary data inputs to the driver are at the
same level.  Such a condition occurs during precharge or in the event
of abnormal signal conditions.  Recognition of the onset of the
finish condition provides self-timing information on the same bus as
data.

      A schematic of the driver is shown in the figure.  Data inputs
INTRUE and INCOMP are complementary inputs such as those obtained
from differential cascode voltage switch (DCVS) logic.  When both
inputs are at their precharged low value near ground, PFETs P1 and P2
are on, PFET P0 is off, and NFET N0 is off.  Devices P1 and P2
connect the OUTPUT terminal to input V2.  Input V2 is at a fixed
spacer voltage approximately equal to VDD/2.

      For a logic 1 input, INTRUE rises to a high level near VDD and
INCOMP remains near ground.  Device P1 turns off, inverter I0 turns
P0 on to pull the single-ended OUTPUT from VDD/2 to VDD, and the
OUTPUT represents a logic 1.  For a logic 0 input, INTRUE remains
near ground and INCOMP rises to VDD.  P1 is on, P2 turns off, P0
turns off, and N0 turns on to pull th...