Browse Prior Art Database

CMOS Chip Temperature Ramp Up Control

IP.com Disclosure Number: IPCOM000105494D
Original Publication Date: 1993-Aug-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Sager, GS: AUTHOR

Abstract

The subject of this disclosure is a method to control the warm up rate of a very large high power dissipation CMOS chip. Large chips which are bonded with many C4 connections having a large distance to a neutral point will create stress on these connections if the chip warms up at a rate faster than the substrate to which it is mounted. This differential temperature created during the initial seconds of power-on can be substantial. Power supply ramping was an effective technique for bipolar transistor circuits. With CMOS circuits which have very little static DC current requirements other methods must be used.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

CMOS Chip Temperature Ramp Up Control

      The subject of this disclosure is a method to control the warm
up rate of a very large high power dissipation CMOS chip.  Large
chips which are bonded with many C4 connections having a large
distance to a neutral point will create stress on these connections
if the chip warms up at a rate faster than the substrate to which it
is mounted.  This differential temperature created during the initial
seconds of power-on can be substantial.  Power supply ramping was an
effective technique for bipolar transistor circuits.  With CMOS
circuits which have very little static DC current requirements other
methods must be used.

      The method suggested here is to control the clock rate of the
CMOS chip/circuits such that the average power during the first
seconds of operation can be ramped, and the power dissipation
controlled.  Several methods are available to accomplish this:

1.  The system clock can be intermittently cycled at full rate.
2.  The system clock can be intermittently cycled based on a
    predetermined duty cycle.
3.  The system clock frequency can be ramped up in frequency
    following a predetermined function.
4.  The system clock frequency can be ramped, or intermittently
    cycled at an adaptive rate based upon temperature feedback from a
    sensor on the substrate and/or chip.