Browse Prior Art Database

Power Management Sleep-Mode Control for Microprocessors

IP.com Disclosure Number: IPCOM000105500D
Original Publication Date: 1993-Aug-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 78K

Publishing Venue

IBM

Related People

Moore, CK: AUTHOR

Abstract

Power management is an important aspect of modern microprocessors. This disclosure addresses a control mechanism for one aspect of power management called "sleep-mode". For the purpose of describing this invention, the concept of "sleep-mode" involves putting the microprocessor in a state of low power during periods of non-use, and "waking-up" the processor as a function of system demand. This technique is implemented in the IBM PowerPC* 601 Microprocessor, however the principles disclosed can be easily adapted to any microprocessor design.

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This is the abbreviated version, containing approximately 52% of the total text.

Power Management Sleep-Mode Control for Microprocessors

      Power management is an important aspect of modern
microprocessors.  This disclosure addresses a control mechanism for
one aspect of power management called "sleep-mode".  For the purpose
of describing this invention, the concept of "sleep-mode" involves
putting the microprocessor in a state of low power during periods of
non-use, and "waking-up" the processor as a function of system
demand.  This technique is implemented in the IBM PowerPC* 601
Microprocessor, however the principles disclosed can be easily
adapted to any microprocessor design.

      This technique requires that several features be included in
the design of the microprocessor.  All of these features have utility
beyond their contribution to the "sleep-mode" control, and therefore
are a reasonable set of design requirements.  The required features
are as follows:

1.  An ability for software to write an address into a register
    (called the stop-on-address register), which when matched by the
    current Instruction Address Register (IAR) of the processor will
    cause the processor to initiate a "soft-stop".  A "soft-stop" is
    achieved after the processor halts dispatch of new instructions,
    waits for the completion of all outstanding instructions, informs
    the system interface that it intends to soft-stop, receives
    permission from the system interface to soft-stop, and then stops
    the processor clocks in a non-destructive manner.

2.  An ability for external logic to present a serial command via the
    Engineering Support Processor which will cause the processor to
    initiate a "soft-stop" as defined above.

3.  An ability for external logic to either assert a single wire or
    to present a serial command using the Engineering Support
    Processor (ESP) interface which will cause the processor clocks
    to be restarted.

      These features allow the system designer to exploit the power
saving advantages of a sleep mode in a relatively simple manner.  The
software can be structured such that when no other tasks are
scheduled to...