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Low Pincount Parametric and Burn-In Test Methodology

IP.com Disclosure Number: IPCOM000105513D
Original Publication Date: 1993-Aug-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 74K

Publishing Venue

IBM

Related People

Williams, RR: AUTHOR

Abstract

Chip pincounts are starting to exceed the number that available testers can probe. In addition, chips need to be burned in (run at elevated temperatures and voltage), and it is desirable that a cheap (i.e., low pincount) module be available to mount the chip on during burn-in.

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This is the abbreviated version, containing approximately 52% of the total text.

Low Pincount Parametric and Burn-In Test Methodology

      Chip pincounts are starting to exceed the number that available
testers can probe.  In addition, chips need to be burned in (run at
elevated temperatures and voltage), and it is desirable that a cheap
(i.e., low pincount) module be available to mount the chip on during
burn-in.

      Many very large-scale integration (VLSI) chips support very
high I/O counts through an array of connections to the chip.  IBM
calls this the "C4" (Controlled Collapse Chip Connection) technology.

      New technologies have a limited number of chip pins from which
all the chip internals can be tested.  This is supported by a
technique called boundary scan.  With boundary scan, with the
exception of the limited number of special pins, all inputs come
through a receiver into a latch.  Also, all outputs must have a latch
before the driver.  These latches are scannable so that data can be
scanned in (through the special pins) into these latches, providing
input/output data without having to actually contact the C4 pins at
wafer probe.  In addition, the most recent technologies require ALL
of the non-special I/Os to be "common I/O", including both a driver
and a receiver.  This allows a technique called "Low Contact Testing"
to be done at wafer probe.  One must test that the driver drives and
the receiver receives.  With the boundary scan in place and with all
of the non-special I/O designed as common I/O, each of the
non-special pins can be tested by providing data at the driver input
and making sure it is received at the receiver.  This tests the
driver and receiver logically, but does not test for "parametrics"
(leakage, pulldown/pullup resistors, switch levels).

      The "low contact testing" methodology requires that the chips
be diced from the wafer and mounted on a temporary carrier for
parametric testing and burn-in.  This temporary carrier must be
capable of handling the total I/O of the chip.  This I/O count now
e...