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RISC Superscalar Parametric Processor Modeller

IP.com Disclosure Number: IPCOM000105520D
Original Publication Date: 1993-Aug-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 6 page(s) / 219K

Publishing Venue

IBM

Related People

Gariazzo, RE: AUTHOR

Abstract

When designing a Central Processor Unit (CPU), there exists the problem of predicting its behavior, especially if the Central Processor Unit is the implementation of a new algorithm. Many of the decisions taken during its design and implementation had to be taken before the actual implementation has begun, or very early in the implementation cycle.

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RISC Superscalar Parametric Processor Modeller

      When designing a Central Processor Unit (CPU), there exists the
problem of predicting its behavior, especially if the Central
Processor Unit is the implementation of a new algorithm.  Many of the
decisions taken during its design and implementation had to be taken
before the actual implementation has begun, or very early in the
implementation cycle.

      With the complexity brought into the CPU design by parallelism
and multiplicity of processing paths, it has becomes very difficult,
or almost impossible, to predict the behavior of such a CPU pipeline
when considering the environment in which the CPU will be part of.

      These predicaments have produced a need not only for tools that
predict behavior, but also the need for tools that are flexible to
evolve with the design, and even more flexible to study deviations
from the main line design.

      The tool presented is a modelling methodology that, starting
from a basic description of the Pipeline Algorithm, allows the
flexibility to grow in complexity in multiple directions.  This
multiplicity not only delivers a powerful tool to study the proposed
design, but also permits very detailed studies of possible variations
for choosing the best compromise between complexity, cost, and
performance.

      The strategy for the "RISC Superscalar Parametric Processor
Modeller" was one of flexibility, growth, and preciseness.  The tool
was implemented with the basic structure of the Superscalar
algorithm, plus all the basic concepts of the stages that form part
of this system, i.e., Fixed Point Unit decode stage, execution
stages, etc.  Once this basic structure and these basic capabilities
were in place, then the incorporation of the model customization was
done.   Each characteristic of the Super Scalar algorithm, plus any
special characteristics of each stage of the pipeline were added on
top of the basic model.  These internal definitions of the pipeline
were implemented and exposed to the user.  In this manner, each of
these special characteristics could be modified to simulate several
configuration of the same basic concept.  Also, parameters were added
to these definitions to create a more flexible tool.  Finally the
tool was surrounded by an interface layer to improve usability.

      The "Superscalar Parametric Processor Modeller" is a CPU
modelling tool including:  Fixed Point Unit(s), Floating Point
Unit(s), a Branch Processor, Instruction Fetcher, the Superscalar
stage, and the Data and Instruction caches.  Every aspect of the
model defined into this tool is parameterized through a "parameter"
file that is read at execution time.  Once the tool has configured
the system to be modelled, it reads from a second data set
instructions to be routed through the pipeline.  After the last
instruction has cleared from the pipeline, the tool prints a report
which is a summary of the instruction trace exe...