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Implementation Of A Partial Write-Back In A WI/WI Hierarchy

IP.com Disclosure Number: IPCOM000105524D
Original Publication Date: 1993-Aug-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 112K

Publishing Venue

IBM

Related People

Rechtschaffen, R: AUTHOR

Abstract

The implementation mechanisms of a partial write-back between two WI levels of a memory hierarchy are disclosed and the inherent advantages described.

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Implementation Of A Partial Write-Back In A WI/WI Hierarchy

      The implementation mechanisms of a partial write-back between
two WI levels of a memory hierarchy are disclosed and the inherent
advantages described.

      Summary statistics from processor organizations suggest that as
the level of multiprocessing increases an advantage should be taken
of the Write-In L1-Level.  Traffic can further be decreased using a
partial write back capability.  The use of partial write-backs in a
WI/WI memory hierarchy provide for a faster processing of a miss when
the line is held exclusive within another processor cache.  The full
line transfer to the requester is the result of a coordinated
operation between the holding L1-CACHE and the L2-CACHE.  Several
performance options present themselves in such a situation.

      Let us consider a Multiprocessing System that is implemented
with a memory hierarchy that is made up of a WI (Write In) L2 cache
and WTWAX (Write Through Write Allocate Exclusive) L1 caches.

A WTWAX cache management protocol is defined as:

o   all stores are written through the L1 cache to the L2 (WT),
o   all lines that are stored into by the processors must be
    allocated (WA - WRITE ALLOCATE), and
o   all lines written into must be held exclusively (X).

      In such caches the DW store rate is .33 STORES/INSTRUCTION and
the aggregate store rate for 16 processors, attached to a single L2,
can easily exceed 2 DW-STORES/CYCLE.  In contrast a memory hierarchy
which is WI, Write In at both the L1 and the L2 level does storing on
a Cast-Out basis.  A CAST-OUT from a WI cache is said to occur when a
line that has been modified is chosen for replacement.  The aggregate
store rate is diminished in the uniprocessor to a cast-out every 4
cache misses.  The miss rate being determined by the cache size.
Thus, with a L1-MISS every 25 instructions, and a cast-out every 100
instructions, the DW STORE rate for 16 processors attached to a
single L2 could be 1 DW-STORES per cycle.  The reason for the
disparity between the DW-STORE rates is that multiple store
opportunities present themselves to the same DW within its sojourn
time in the cache.

      The use of partial write-backs in a WI/WI memory hierarchy
provide for a further reduction in DW traffic between the L1-L2
caches, for a faster handling of the cast out that is commensurate
with the shorter latency time of the L2-CACHE, and for a faster
processing of a miss of another processor when the line is held
exclusive within a remote cache.  CLEARING THE CASTOUT DURING THE
L2-CACHE LATENCY

      One central advantage of the partial writeback is the ability
to clear the modified portions of the line into a cast-out buffer in
a shorter time interval.  This allows the L2-LEVEL, which has a short
latency time, to begin transferring the miss to the L1 cache earlier.
In prior designs of a WI-L1 CACHE, the L1 was supported by an L3
which had a long lat...