Browse Prior Art Database

Parity Error Address Display Card

IP.com Disclosure Number: IPCOM000105531D
Original Publication Date: 1993-Aug-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 83K

Publishing Venue

IBM

Related People

Holness, SE: AUTHOR [+2]

Abstract

Disclosed is a circuit card, configured for installation in a Micro Channel* slot of a personal computer, which includes an LED display providing a hexadecimal indication of the higher-order memory address bits and the arbitration bits when a parity error occurs.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Parity Error Address Display Card

      Disclosed is a circuit card, configured for installation in a
Micro Channel* slot of a personal computer, which includes an LED
display providing a hexadecimal indication of the higher-order memory
address bits and the arbitration bits when a parity error occurs.

      The detection of a parity error generally causes a system to
halt the execution of code without providing any information
concerning the location of the error.  However, in the IBM Personal
System/2* Systems, Models 70 and 80, information is present on the

Micro Channel bus for capturing a partial address of the failing
memory location when a parity error occurs.  In these systems, a
system board parity error simultaneously generates an I/O CHANNEL
CHECK signal sent to the Micro Channel bus and an NMI (Non-Maskable
Interrupt) signal sent to the processor.  Thus, it is possible to
determine, in circuits operating from the Micro Channel bus,
precisely when a parity error occurs.

      During a processor access to the system board memory, at most
only part of a full Micro Channel cycle is executed.  On a system
board memory page hit, no control signal and no address or data
information is sent to the Micro Channel bus.  However, in Personal
System/2 Models 70 and 80, a memory access from the processor to the
system board, on a memory page miss, will send a valid address to the
Micro Channel bus, along with a status control signal, which is
activated before the Micro Channel cycle is aborted.  This signal,
along with the I/O CHANNEL CHECK signal, is used to latch the memory
address in the address display card.

      All other types of memory cycles, such as busmaster cycles to
system memory, processor cycles to channel memory, and busmaster
cycles to channel memory, run full Micro Channel cycles, allowing the
address display card to latch valid addresses.  Channel memory errors
also result in an I/O CHANNEL CHECK signal, which causes the memory
address to be stored in the address display card.

      The logic of the address display card is schematically shown in
the figure.  The va...