Browse Prior Art Database

Prefetching for Multiple Targets Concurrently

IP.com Disclosure Number: IPCOM000105533D
Original Publication Date: 1993-Aug-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 4 page(s) / 87K

Publishing Venue

IBM

Related People

Rechtschaffen, R: AUTHOR

Abstract

The prefetching requirements for a simple recursive loop can be satisfied by a slight extension to the prefetching command that eliminates all the traffic associated with a miss. The means of accomplishing this is disclosed.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Prefetching for Multiple Targets Concurrently

      The prefetching requirements for a simple recursive loop can be
satisfied by a slight extension to the prefetching command that
eliminates all the traffic associated with a miss.  The means of
accomplishing this is disclosed.

Consider the following loop:

   LOOP  L   R1, D1(R1)
         TM  X'FF', D2(R1)
         BE  LOOP

This loop can be visualized as a  process that chains through a set
of control blocks.

o   The register R1 holds a pointer (PTR) to the control block.
o   The control block has a PTR to the next control block,
    NEXT.PTR.LOCATION, in the chain at a displacement D1 from the
    position addressed by the PTR, PTR.VALUE.
o   The control block has a TEST.BYTE at a displacement D2 from the
    position addressed by the PTR, PTR.VALUE.

Assume that a prefetching mechanism exists which is assisted by a GLT
within the processor.

GLT - Let us consider the GPR LOCATION TABLE (GLT) which for each of
the 15 GPR that can be used for Address Generation (AGEN) contains,
if valid, the address from which the current contents of the GPR was
LOADED.  Entries within this GLT are invalidated by any instruction
that modifies the value of the GPR associated the entry.  The entry
in the GLT is made at the time of the AGEN operation of the LOAD
instruction which places the value from memory at the location
specified by entry into the associated GPR.  Thus LOAD operations
invalidate the GLT entry but not until it is determined that the LOAD
has not caused a D-CACHE MISS.  In this context the LM is considered
a series of LOAD instructions and the ADDRESSES inserted in the GLT
are the addresses of the 4-BYTE WORDS from which the registers are
loaded.  If the source register of a LR instruction has a valid entry
in the GLT then the entry within the GLT that corresponds to the sink
register is updated appropriately.

      At the point of a D-CACHE miss, and with a valid GLT entry for
the register used in the Address Generation (AGEN) the processor
supplies:

o   the location from which the GPR was loaded.
o   the value found of the GPR, and
o   the address of the target of the D-CACHE miss, to a
    miss-monitoring mechanism within the L2.

OPERATION OF TH...