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Improved Partial Store Function

IP.com Disclosure Number: IPCOM000105534D
Original Publication Date: 1993-Aug-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 4 page(s) / 88K

Publishing Venue

IBM

Related People

Getzlaff, K: AUTHOR [+4]

Abstract

Fig.1 shows a level-1 cache 20 connected on one side directly to a processor 10 and on the other to a main memory 70. Main memory 70 has a data-in register 80 and a data-out register 60 together with an address register 100. Level-1 cache 20 has a data-in register 30. The address resolver 110 determines whether the data required by pro cessor 10 is present in cache 20 or in main memory 70. Associated with main memory 70 is a check bit generator 90 which generates check bits to be stored with the data in main memory 70 and an error checking and correcting unit 50 which uses the stored check bits to check the data being read out of main memory 70 and correct it if required. The corrected data is passed through a multiplexer 40 to data-in register 30 whence it is read into level-1 cache 20.

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Improved Partial Store Function

      Fig.1 shows a level-1 cache 20 connected on one side directly
to a processor 10 and on the other to a main memory 70.  Main memory
70 has a data-in register 80 and a data-out register 60 together with
an address register 100.  Level-1 cache 20 has a data-in register 30.
The address resolver 110 determines whether the data required by pro
cessor 10 is present in cache 20 or in main memory 70.  Associated
with main memory 70 is a check bit generator 90 which generates check
bits to be stored with the data in main memory 70 and an error
checking and correcting unit 50 which uses the stored check bits to
check the data being read out of main memory 70 and correct it if
required.  The corrected data is passed through a multiplexer 40 to
data-in register 30 whence it is read into level-1 cache 20.  Level-1
cache 20 has no error checking mechanism associated with it.  From
level-1 cache 20, the data can be passed to processor 10.

      A store-through operation is carried out by sending data from
processor 10 to data-in register 30 through a store aligner (not
shown).  This data is written into cache memory 20, overwriting
changed bytes.  The data has also to be written into main memory 70
and this function is carried out by the circuit shown in Fig. 2.

      The purpose of this circuit is to merge the changed data bytes
from processor 10 with unchanged data bytes present in cache memory
20 to form a complete word which can be supplied to main memory 70.
In Fig.  2, in the horizontal direction, the width of cache 200 is
shown.  It comprises, i...