Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Single-Latch Element Modeling Technique

IP.com Disclosure Number: IPCOM000105562D
Original Publication Date: 1993-Aug-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Kahle, JA: AUTHOR [+2]

Abstract

This invention pertains to modelling "master/slave LSSD latches" in a manner which allows for efficient simulation of large systems using many such latches. The technique allows the pair of latches to be modelled as a single latch element which effectively reduces the amount of work the simulator needs to do in the course of simulating the system behavior during each cycle. Since the development of complex VLSI designs demand large amounts of simulation, the effective savings in terms of real CPU hours used for simulation and the productivity gain due to faster simulation job turn around time is quite large.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 56% of the total text.

Single-Latch Element Modeling Technique

      This invention pertains to modelling "master/slave LSSD
latches" in a manner which allows for efficient simulation of large
systems using many such latches.  The technique allows the pair of
latches to be modelled as a single latch element which effectively
reduces the amount of work the simulator needs to do in the course of
simulating the system behavior during each cycle.  Since the
development of complex VLSI designs demand large amounts of
simulation, the effective savings in terms of real CPU hours used for
simulation and the productivity gain due to faster simulation job
turn around time is quite large.

      In a compiled-based cycle simulator, the entire network needs
to be "ranked-ordered" or "leveled" such that a particular signal is
scheduled for evaluation before it can be used to evaluate another
signal that it may affect.  Each "clock" cycle, the entire network
must be analyzed.  Master/Slave LSSD latches modelled in a
conventional manner would require TWO clocks to a show data
propagating through them - one for the L1 latch and one for the L2
latch.  By modeling these latches as single latch element, we require
only a signal clock cycle to show data propogating through them.  The
effect is to double the simulation efficiency of the effort.

      The particular technique disclosed here assumes a latch and
clocking structure as shown in Fig. 1, although similar techniques
can be applied to other...