Browse Prior Art Database

Processor Synchronization Circuitry for Computer Systems

IP.com Disclosure Number: IPCOM000105577D
Original Publication Date: 1993-Aug-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 4 page(s) / 91K

Publishing Venue

IBM

Related People

Dean, ME: AUTHOR [+3]

Abstract

Described is a circuit implementation that provides a means of synchronizing one or more processors to a given clock phase of the computer system's clock. The circuit uses slow speed integrated circuits to accomplish the synchronization.

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This is the abbreviated version, containing approximately 52% of the total text.

Processor Synchronization Circuitry for Computer Systems

      Described is a circuit implementation that provides a means of
synchronizing one or more processors to a given clock phase of the
computer system's clock.  The circuit uses slow speed integrated
circuits to accomplish the synchronization.

      Typically, after a processor has been reset, during normal
computer operations, it must be synchronized to the clocking phase of
the overall system clock.  With many processors used in a computer
system, it is essential that the timings of the processors be closely
synchronized.  In prior art, extensive logic circuitry was required
to provide this synchronization.  The concept described herein
eliminates the extensive logic circuitry by providing synchronization
utilizing slower speed devices.

      Fig. 1 shows a basic block diagram of a typical system.  A high
speed clock signal is distributed to the associated processor through
a clock driver (not shown).  Fig. 2 shows a timing diagram of the
oscillator (OSC), the clock driver outputs (CLK2) and clock (CLK)
signals during a RESET operation.  Typically, the clock driver will
have one or more reset request inputs (not shown) which are
asynchronous to the oscillator which will cause an occurrence of a
reset operation.  The clock driver sends two outputs to each
processor, CLK2 and RESET.  Each processor divides the CLK2 frequency
by a factor of 2 to generate CLK.  In order to obtain proper system
operation, the two phases CLK must be synchronized for each
processor.

      The concept described herein accomplishes the synchronization
by interrupting the CLK2 periodicity.  The CLK2 signal is used to
maintain a zero for two OSC periods.  During this time, a reset
signal is sent to one or more of the processors in the system.  The
next positive CLK2 pulse edge is recognized by the processor(s) as
the start of Phase 1.  By using th...