Browse Prior Art Database

Advanced I/O Structure in a Hierarchical Multiprocessor System

IP.com Disclosure Number: IPCOM000105588D
Original Publication Date: 1993-Aug-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 4 page(s) / 122K

Publishing Venue

IBM

Related People

Booth, RC: AUTHOR [+5]

Abstract

As the number of processors contained in the central processor complex of a shared storage computer system continue to grow, the overall bus bandwidth required between the processors, shared main storage, and I/O also continue to grow. In a tightly coupled multiprocessor topology, the shared bus eventually becomes the performance bottleneck of the system. This bottleneck is known as the Von Neumann bottleneck. Described is a method for increasing multiprocessor system performance, beyond the limit imposed by the Von Neumann bottleneck, by employing an advanced I/O structure in a hierarchical multiprocessor system.

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Advanced I/O Structure in a Hierarchical Multiprocessor System

      As the number of processors contained in the central processor
complex of a shared storage computer system continue to grow, the
overall bus bandwidth required between the processors, shared main
storage, and I/O also continue to grow.  In a tightly coupled
multiprocessor topology, the shared bus eventually becomes the
performance bottleneck of the system.  This bottleneck is known as
the Von Neumann bottleneck.  Described is a method for increasing
multiprocessor system performance, beyond the limit imposed by the
Von Neumann bottleneck, by employing an advanced I/O structure in a
hierarchical multiprocessor system.

One possible multiprocessor (MP) topology for increasing the number
of processors, and hence system performance, beyond the limit imposed
by the Von Neumann bottleneck is to employ a hierarchical bus
structure.  This structure connects processors via a shared main
storage bus in sets of small numbers of processors called nodes and
then interconnects sets of nodes via a shared global bus.  All I/O in
such a system is then connected via the shared global bus.
Eventually, as in the case of the tightly coupled MP topology, the
global bus will become the system performance bottleneck as predicted
by the Von Neumann bottleneck.

      This disclosure addresses the system performance bottleneck
inherent in the hierarchical bus structure by providing a physically
separate data and control path for all system I/O transfers.
Providing a separate I/O interconnection removes traffic from the
shared global main storage bus.  With I/O traffic removed, additional
processors, either within a processor node or adding additional
nodes, can be included to farther increase system performance.

      This disclosure introduces the concept of a "Bank of I/O
Processors (IOPs)", heretofore referred to as an I/O bank.  An I/O
bank is that set of I/O processors and their respective I/O devices
that are connected via a single system I/O adapter.  In our solution,
multiple I/O banks are supported at the ratio of 1 I/O bank per
processor node.  The number of processors in a node and the number of
IOPs in an I/O bank are variables while holding the 1 to 1 ratio
between processor nodes and I/O banks constant.

      As stated, a given I/O bank has one I/O adapter.  This I/O
adapter is connected to the shared main storage bus contained within
a processor node, referred to as the local main storage bus.  A
global I/O interconnection is also included which interconnects all
I/O banks in the system.  This is the separate I/O interconnection
that removes I/O traffic from the global main storage bus and allows
for increased system performance.

      Symmetrical I/O is provided by our structure.  Symmetrical I/O
allows any processor in the system to initiate an I/O operation with
a DMA transfer to/from any I/O device connected to the system with
the subsequent I/O...