Browse Prior Art Database

Tester-Loaded Simulation

IP.com Disclosure Number: IPCOM000105602D
Original Publication Date: 1993-Aug-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 6 page(s) / 199K

Publishing Venue

IBM

Related People

Stewart, BA: AUTHOR

Abstract

A mode of board level simulation is disclosed which accounts for the fact that the electrical characteristics of a circuit on a printed circuit board change as it is physically probed during test. The loading phenomenon is described along with the effects on expected responses to applied test stimuli. Disclosed is a method for determining if tester loading will significantly affect at-speed functional test and minimizing tester loading effects.

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This is the abbreviated version, containing approximately 32% of the total text.

Tester-Loaded Simulation

      A mode of board level simulation is disclosed which accounts
for the fact that the electrical characteristics of a circuit on a
printed circuit board change as it is physically probed during test.
The loading phenomenon is described along with the effects on
expected responses to applied test stimuli.  Disclosed is a method
for determining if tester loading will significantly affect at-speed
functional test and minimizing tester loading effects.

      As designs push the limits of technology, the potential effects
of minor variations in the electrical characteristics of a circuit
become more pronounced.  When a card is physically contacted during
test, the test probes have the effect of adding capacitive load to
the probed net.  This additional load causes the rise and fall delays
of the net to differ from those of an unloaded card.  Therefore,
during functional test, the captured response may differ from the
expected response, even when the card under test is good.  Simulation
of functional test patterns can be used to determine the expected
response of a card during functional test.  However, the model of the
circuit does not take into account the effects of tester loading on
circuit operation.  I have invented a novel mode of board level
simulation, tester loaded simulation.  Tester loaded simulation
operates on a circuit model which represents the card in a tester
loaded environment.  This results in reduced effort to bring a high
quality at-speed functional test on-line, reduces the chance of a
good card being tested as faulty and in some cases, prevents faulty
cards from passing functional test due to tester loading effects.

      Any given card design has a set of electrical characteristics
associated with it.  Among these characteristics is the set of net
delays for each net on the board.  During card level test, a card may
be physically contacted via test probes in order to observe and/or
stimulate various nets.  When a test probe makes contact with a net
on the card, the electrical characteristics of that net change.  The
loads associated with the test probe, the lead to the probe, and the
driver/sensor circuitry now have an effect on the net load.  We
define this effect as tester loading.

      In its simplest form, tester loading can be modeled as
additional capacitance on a net.  A typical capacitance for a probe,
lead and fixture interface might be 20-30pF.  Typical numbers are
15pF/ft for twisted pair and 30pF/ft for coax.  This capacitance has
the effect of increasing the rise and fall times of signals on the
probed net when compared with the normal non-tester loaded net
delays.  For the purposes of this paper, the only tester loading
effect which we will address is that of additional net delays.

      Are these tester induced delays a cause for concern?  As
advances in card technology are implemented, the probability that
tester loading effects will ca...