Browse Prior Art Database

Interleaved Memory Dual Bus Data Selector

IP.com Disclosure Number: IPCOM000105615D
Original Publication Date: 1993-Aug-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 76K

Publishing Venue

IBM

Related People

Alderequia, AA: AUTHOR [+6]

Abstract

Described is an architectural logic implementation for personal computers (PCs) to provide an interleaved memory dual bus data selector to improve system performance and to eliminate bus contentions between microprocessors, memories, and feature buses.

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This is the abbreviated version, containing approximately 52% of the total text.

Interleaved Memory Dual Bus Data Selector

      Described is an architectural logic implementation for personal
computers (PCs) to provide an interleaved memory dual bus data
selector to improve system performance and to eliminate bus
contentions between microprocessors, memories, and feature buses.

      Typically, PC designs require high speed data transfer
capabilities between the microprocessor, the memory subsystem, and a
feature bus, such as the Micro Channel* (MC).  This requires the
microprocessor to constantly retrieve code or data from the memory
subsystem.  In addition, the memory is interleaved for performance
enhancement.  The MC generally contains DASD and high baud rate
device bus masters, such as video controllers, to transfer large
blocks of data either to or from memory.  Although the microprocessor
may have an internal, or an external cache, the microprocessor may be
locked out of the memory path for periods of time while a bus master
is accessing memory.  As a result, this lock out can reduce system
performance.

      The described concept improves on the performance
characteristics through the use of a dual bus data selector.  Fig. 1
shows the architectural arrangement with three buses:  CPU, system.
and memory data buses.  Transfers between buses are possible between
- the CPU to/from memory, - the CPU to/from the MC, and - the MC
to/from memory.  Each bus is controlled independently which allows
for data transfers on the buses simultaneously.  To increase memory
access performance, the memory data bus is designed to support two
way interleaving.  In addition, the memory interface must support the
generation of error correction or parity bits.

      Fig. 2 shows the data steering portion of the system using only
five 32-bit transreceiver macros.  Both the CPU and the system buses
require two 32-bit transreceivers for connecting to the memory ports
to implement the two way interleave.  The fifth transreceiver is used
to provide a high performance data path between the CPU...