Browse Prior Art Database

Local Transfer Bus Architecture for Personal Computer Control Adapters

IP.com Disclosure Number: IPCOM000105628D
Original Publication Date: 1993-Aug-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 4 page(s) / 145K

Publishing Venue

IBM

Related People

Voorhees, RW: AUTHOR

Abstract

Described is an architectural implementation to provide a local transfer bus (LTB) to enable a number of circuit modules to be interconnected onto a single attachment circuit card for use with various personal computer (PC) control adapters.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 36% of the total text.

Local Transfer Bus Architecture for Personal Computer Control Adapters

      Described is an architectural implementation to provide a local
transfer bus (LTB) to enable a number of circuit modules to be
interconnected onto a single attachment circuit card for use with
various personal computer (PC) control adapters.

      In prior art, a number of different control adapter circuit
cards were required for a wide range of applications resulting in
design trade-offs for implementation.  For example, a disk controller
had trade-offs to consider, such as the number devices to be
supported, cache vs no-cache, raw data rate, local processor speed or
overhead, and the number of separate small computer system interface
(SCSI) buses to be used.  Since most of the circuits were
specialized, the trade-offs had to be rigidly defined before any
circuit design began.  However, due to changing market conditions,
designs often changed so as to cause existing designs to become
obsolete.  Also, plans for multiple products were required in order
to address a wider market.  As a result, it was desirable to have
circuits interchangeable between the various designs so as to reduce
the amount of development time and expense.  Specifically, a way was
needed to implement major functions for interconnection in a
"mix-and-match" way to allow adapters to be easily built so as to
support a variety of designs.

      The concept described herein is intended to provide
interchangeable and flexible architecture and yet be compatible with
existing circuit and processor designs.  The LTB enables the use of a
wide variety of circuits to be selected for a particular card with
final card design points under consideration, such as the use of
different microprocessors, cache vs non-cache, one SCSI bus vs two,
etc.  Each circuit is designed so that it can communicate with any,
or all, of the other circuits on the card.

      The LTB is an implicit bus where the source and destination of
the data are known and no address is associated with transfers.  This
type of bus employs a form of request/acknowledge (REQ/ACK) protocol.
One circuit initiates a transfer by presenting a REQ and the other
completes the transfer by responding with an ACK.  Fig. 1 shows a
typical LTB timing waveform and Fig. 2 lists the bus timing values of
the LTB protocol.  Typically, assignments are wired-in the logic
circuits and are not changeable.  However, the LTB is designed to
function with a variety of existing circuits so that new designs
which employ the LTB can function with existing circuitry.  This
functionality is enabled by making the software configurable.  By
utilizing configurable software, it allows the circuit microcode to
configure a circuit so that it can communicate with another circuit
which may not be as flexible.  The microcode is used to set up the
LTB bus control register.  Fig. 3 shows a block diagram of the LTB
bus control register.  The bits in the...