Browse Prior Art Database

Decode Compound Checker

IP.com Disclosure Number: IPCOM000105647D
Original Publication Date: 1993-Aug-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 85K

Publishing Venue

IBM

Related People

Blaner, B: AUTHOR [+2]

Abstract

In a typical SCISM processor, instructions are examined for parallel execution prior to instruction decode, for example during cache-miss processing. Instructions identified for parallel execution are called a compound instruction. This information is stored with the instructions as additional tag bits in the cache. A diagram of a compound instruction cache and instruction buffer are shown in the figure. As text is loaded from memory on a cache miss, it passes through the compounder. The compounder may consist of a buffer and one or more copies of compound rule circuitry known as a C-box, depending on the performance requirements. As instructions are processed, the tag bits specify which instructions can be executed in parallel, simplifying the instruction decode process.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Decode Compound Checker

      In a typical SCISM processor, instructions are examined for
parallel execution prior to instruction decode, for example during
cache-miss processing.  Instructions identified for parallel
execution are called a compound instruction.  This information is
stored with the instructions as additional tag bits in the cache.  A
diagram of a compound instruction cache and instruction buffer are
shown in the figure.  As text is loaded from memory on a cache miss,
it passes through the compounder.  The compounder may consist of a
buffer and one or more copies of compound rule circuitry known as a
C-box, depending on the performance requirements.  As instructions
are processed, the tag bits specify which instructions can be
executed in parallel, simplifying the instruction decode process.

      There are two potential problems with the compounder
organization as described above.  If there are stores into already
compounded instructions the compound tag may no longer be correct.
Solutions to this such as invalidating the cache line or
recompounding all or part of a cache line are possible but the
relative low frequency of stores into instructions suggests another,
simpler solution.  A second problem with compounding is that hardware
errors in the C-box are not detected.  In both these cases, a
compound tag specifying no parallel execution errs on the safe side;
there is a potential performance loss but execution is correct.  A
compound tag specifying parallel execution when it is not possible
can lead to incorrect execution which may not be detectable by the
instruction execution hardware.

      This article discloses a solution to either or both of these
problems.  As shown in the figure another box is added to the
processor organization.  The new hardware is known as the Decode
Compound Checker (DCC) and consists of another copy of the C-box
logic.  In parallel with instruction execution, DCC checks whether
the instructions should really be compounded.  The timing
requirements for this compounder are that it must complete before the
instructions finish and update the processor state.  Typically the
compounder is a one-cycle operation so this is not a concern.  The
compounder runs in parallel with...