Browse Prior Art Database

Full-Cache Diskette Drive

IP.com Disclosure Number: IPCOM000105659D
Original Publication Date: 1993-Aug-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Waldron, RA: AUTHOR

Abstract

This article describes how to speed up access time between the CPU and a diskette to achieve system Bus data rates.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 69% of the total text.

Full-Cache Diskette Drive

      This article describes how to speed up access time between the
CPU and a diskette to achieve system Bus data rates.

      The existing configuration for a diskette controller is a CPU
connected through a relatively small sector buffer to a diskette
magnetic storage medium.  In the existing systems, the small sector
buffer is typically on the order of 1 Kbyte of RAM.  The RAM is
connected to the system bus and typically communicates with the
system RAM by means of a DMA (Direct Memory Access) unit.  In
existing systems, the I/O bus data rate is 10 megabits per second.
Whenever a diskette access is required, a 1 Kbyte block can be
transferred from the diskette to the system RAM through the sector
buffer.  If another access of the diskette requires the accessing of
data in a portion of the diskette which is not a part of the original
contiguous 1 Kbyte, then still another diskette read operation must
take place and the transfer of still another 1 Kbyte block through
the sector buffer must be carried out.  The aggregate delays in
consecutive or multiple diskette accesses can add a substantial delay
to the overall throughput of the CPU operation.  Part of this is due
to the spin rate or latency in performing disk accesses on a
diskette.

      The disclosed invention enlarges the size of the sector buffer
so that it is at least equal to the storage size of the diskette.
Typical diskettes run between 1.4 megabytes and 2.8 megabyt...