Browse Prior Art Database

Integrated Debug Aid

IP.com Disclosure Number: IPCOM000105662D
Original Publication Date: 1993-Aug-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 4 page(s) / 109K

Publishing Venue

IBM

Related People

Braun, R: AUTHOR [+4]

Abstract

This article describes a circuit which permits reading important signals via a serial high-speed interface.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Integrated Debug Aid

      This article describes a circuit which permits reading
important signals via a serial high-speed interface.

      In more complex integrated (VLSI) circuits, the ratio of the
internal logic to externally observable nets is increasing.  To be
able to observe as many internal signals as possible, several signals
are applied to output pins.  However, the number of output lines is
greatly limited so that even when using an internal multiplexer only
very few signals may be observed.

      The interface of the circuit covered by this article consists
of two components: a first component which is integrated on the chip
to be tested and which controls the serial data transfer, and a
second com ponent which accommodates and displays the serial data.
The two com ponents are connected by three lines: a request line, a
data line and a clock line.  The request line is used to send a
request to the chip to be tested.  In response, the chip supplies the
necessary clock and data signals for processing this request.  The
second component, which accommodates and displays the data, is
totally independent of the first component and can also be connected
to several chips.  Active control is effected by the logic to be
integrated on the chip.

      The chip-internal logic comprises the following components: a
request recognizer, a sequence control, a counter, a shift register,
and a clock generator.  The request recognizer serves to determine
when data is to be sent and accommodated in the shift register.  Data
may be transmitted in various ways.  The alternative chosen for the
described circuit is such that the request is issued through the
service processor as a command.  As a result, the execution of other
commands coming from the service processor may be observed.

      The sequence control is the central component of the logic to
be integrated on the chip.  The sequence control receives the
synchronized request from the request recognizer.  In response, the
sequence control initially resets the counter and activates the

"busy" signal.  The "busy" signal locks the request recognizer, thus
suppressing further requests during a current data transfer cycle.
After the counter has been reset and the "busy" signal activated, the
data is transferred in parallel to the shift register where it is
subsequently available for serial reading.

      The counter then receives a start pulse, and the clock
generator is switched on.  The clock generator receives its clock
from the internal system clock of the chip to be tested until the
sequence control receives a "s...