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Browse Prior Art Database

GaInAs Superconducting FET

IP.com Disclosure Number: IPCOM000105677D
Original Publication Date: 1993-Aug-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Hodgson, RT: AUTHOR [+2]

Abstract

It is difficult to make superconducting oxide connections to GaInAs, since the high temperatures needed to anneal the superconductor destroy the semiconductor.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

GaInAs Superconducting FET

      It is difficult to make superconducting oxide connections to
GaInAs, since the high temperatures needed to anneal the
superconductor destroy the semiconductor.

      The invention is sketched in the Figure.  A silicon substrate 1
is implanted n++ or p++ in an area 2, and an oxide 3 of Zr, Y, or Sc
is grown epitaxially on top of the silicon.  As the oxide grows,
oxygen diffuses through it to the silicon surface, where it oxidizes
the underlying material to amorphous SiO&sub2  4.  The top oxide
layer, however, "remembers" the underlying silicon registration and
grows a single crystal which is "epitaxial" to the underlying
silicon.  Presumably, we could make the underlying SiO&sub2.  layer
as thick as we wished by stopping the zirconium, yttrium, or scandium
flux and hence stopping further growth of the overlying crystal oxide
material.  At this point, the superconducting material 5 (for example
yttrium barium copper oxide) is laid down and patterned with a gap 6
shown.  Then, a  Ga sub (.2) In sub (.8) As  layer 7 is grown
selectively in the gap epitaxial to the underlying oxide.  Either the
Ga sub (.2) In sub (.8) As will be confined to the gap by selective
deposition or it can spread out over the top of the superconducting
oxide.  Finally, a layer 8 of  Al sub (.2) In sub (.8) As is laid
down to cap the device.