Browse Prior Art Database

Pulse-Width Symmetry Circuit

IP.com Disclosure Number: IPCOM000105678D
Original Publication Date: 1993-Aug-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 75K

Publishing Venue

IBM

Related People

Schmunkamp, D: AUTHOR [+2]

Abstract

A circuit is described which permits an arbitrary clock signal at a path output to be symmetrized independently of the path characteristics.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Pulse-Width Symmetry Circuit

      A circuit is described which permits an arbitrary clock signal
at a path output to be symmetrized independently of the path
characteristics.

      For generating clocks in complex systems, the clock pulses have
to be accurately defined.  A critical parameter is the duty cycle of
the signal which determines the ratio of the pulse width to the
period.  Ideally, the duty cycle should be 50%, i.e., the signal
should have the logical values '0' and '1' for an equal length of
time.

      Previously, the lack of symmetry was compensated for by using
double frequency values for the input signal and by deriving the
output signal from the input signal by dividing by 2, so that the
decisive edges of the output signal were determined by the same edge
of the input signal.  In this case, the resulting minimal inaccuracy
of the output signal is solely determined by the divide stage.

      As clock frequencies increase, this approach is impracticable
for a number of reasons.  To remedy this, a circuit is provided which
uses an additional or an existing output signal 1 of the clock
generator chip CGC.  This signal is fed to an integrator 2.  The
output voltage of the integrator is applied to an amplifier 3 and the
output signal of the latter to an adder 4.  The adder adds the signal
of the oscillator 5 and the output signal of the comparator,
transmitting the result to a further integrator 6.  The output of the
integrator feeds the input of conventional buffer stages.

      The time constant of the integrator 2 noticeably exceeds the
period of the signal (roughly by a factor 100).  As a result, the
output voltage of the integrator is a DC voltage which is
proportional to the duty cycle of the input signal.  For a duty cycle
of 50% the output voltage is half the operating voltage.

      This voltage is compared by amplifier 3 with half the operating
voltage Ub/2.  The amplifier has an ampli...