Browse Prior Art Database

Creation of Simulation Testcases for New Hardware on Previous Generation Hardware

IP.com Disclosure Number: IPCOM000105686D
Original Publication Date: 1993-Aug-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 6 page(s) / 154K

Publishing Venue

IBM

Related People

Spenser, AK: AUTHOR

Abstract

This invention creates simulation testcases by running 'C' code on the RISC System/6000* platform for the followon processor design.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 36% of the total text.

Creation of Simulation Testcases for New Hardware on Previous Generation Hardware

      This invention creates simulation testcases by running 'C' code
on the RISC System/6000* platform for the followon processor design.

      Background - There is a need for executing real code on a
simulation model of a new processor design.  This need exists because
the designers need to verify that the design will work correctly when
the first chips are received.  Also product cycles are getting
shorter and it is critical to the success of a project to have
working chips in one pass of the design.  One way to ensure that the
processor chip set will work the first time, is through system
simulation.  In RISC System/6000 design a Random Test Program
Generator (RTPG) was used to create millions of random testcases that
would be executed on the simulation model.  In the followon design
project we have an opportunity to utilize the RISC System/6000
hardware to generate testcases with expected results for the followon
design.  Since the followon architecture is a super set of the RISC
System/600 architecture, any instructions created on RISC System/6000
should run on the followon architecture.  The testing of the new
instructions must then be done with RTPG.

      Thus, the problem is how to use RISC System/600 to create a
testcase for the followon design.

Solution Follows:

1.  Create a program in 'C'.
2.  Compile the program and create a listing file.
3.  Use the "cavp" shell script to parse the listing file to create a
    'dbx' command file that will allow the program to be executed
    under the UNIX debugger 'dbx'.
4.  Run the program on the RISC System/600 under control of 'dbx'.
5.  Have 'dbx' dump out registers and memory used by the program
    before it starts.  This gives the initial state of the ma chine.
6.  Let the program run.
7.  Have 'dbx' dump out registers and memory used by the program
    after it has run.  This gives the final state of the machine.
8.  Parse the resulting execution history and convert it to a
    followon testcase form.

      The resulting testcase contains an instruction trace, as well
as the initial state of the machine and the resulting state after
execution completes.  This testcase is now ready to run on the
followon model.  The program on RISC System/6000 and if the results
are different when executed on the followon model then a problem in
the followon design has been found.  The 'cavp' program also creates
an 'avplist' which is a file that contains all the required
parameters to the simulator for running the generated testcast.

The benefits follow:

1.  Creates testcases in a fraction of the time required by RTPG,
    since the RISC System/6000 hardware is used to generate the
    expected results.
2.  Can create testcases with more looping constructs than RTPG.
    This then offers additional test coverage for the design.
3.  Executes real code sequ...